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參數(shù)資料
| 型號： | ST10F168-Q3 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 28 X 28 MM, PLASTIC, QFP-144 |
| 文件頁數(shù)： | 52/74頁 |
| 文件大?。?/td> | 479K |
| 代理商： | ST10F168-Q3 |
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ST10F168
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The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes fCPU to keep it
locked on fXTAL. The relative deviation of TCL is
the maximum when it is refered to one TCL
period. It decreases according to the formula and
to the Figure 19 given below. For
N periods of TCL
the minimum value is computed using the
corresponding deviation DN:
where N = number of consecutive TCL periods
and 1
≤ N ≤ 40. So for a period of 3 TCL periods
(N = 3):
D3
= 4 - 3/15 = 3.8%
3TCLmin = 3TCLNOM x (1 - 3.8/100)
= 3TCLNOM x 0.962
3TCLmin = (57.72ns at fCPU = 25MHz)
This is especially important for bus cycles using wait
states and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer
periods (e.g. pulse train generation or measurement,
lower Baud rates, etc.) the deviation caused by the
PLL jitter is negligible (see Figure 19).
20.5.8 - External Clock Drive XTAL1
VDD =5V ± 10%, VSS = 0V, for Q6 version : TA = -40, +85°C and for Q3 version TA = -40, + 125°C, unless
otherwise specified.
Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal.
2. The input clock signal must reach the defined levels VIL and VIH2.
TCL
MI N
TCL
NO M
1
D
N
100
-------------
–
×
=
D
N
4N 15
) %
[]
–
(
±
=
Figure 19 : Approximated maximum PLL jitter
Symbol
Parameter
fCPU =fXTAL
fCPU =fXTAL /2
fCPU =fXTAL xN
N = 1.5 / 2 / 2.5 /3 /4 / 5
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tOSC
SR
Oscillator period
40 1
1000
20
500
40 x N
100 x N
ns
t1
SR
High time
18 2
–6 2
–10 2
–ns
t2
SR
Low time
18 2
–6 2
–10 2
–ns
t3
SR
Rise time
–
10 2
–6 3
–10 2
ns
t4
SR
Fall time
–
10 2
–6 2
–10 2
ns
Figure 20 : External clock drive XTAL1
32
16
8
4
2
±1
±2
±3
±4
Max.jitter [%]
N
This approximated formula is valid for
1 < N < 40 and 10MHz < fCPU < 25MHz.
t1
t3
t4
VIH2
t2
tOSC
VIL
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