參數(shù)資料
型號(hào)： SSTUP32866EC/S
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
封裝： 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96
文件頁(yè)數(shù)： 6/31頁(yè)
文件大小： 538K
代理商： SSTUP32866EC/S
SSTUP32866_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 14 September 2006
14 of 31
Philips Semiconductors
SSTUP32866
1.8 V DDR2-667/800 programmable registered buffer with parity
[1]
This parameter is not necessarily production tested.
[2]
VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken
HIGH.
[3]
VREF, data and clock inputs must be held at valid levels (not oating) a minimum time of tINACT(max) after RESET is taken LOW.
[1]
Includes 350 ps of test load transmission line delay.
[2]
This parameter is not necessarily production tested.
Table 10.
Timing requirements
At recommended operating conditions (see Table 8), unless otherwise specied. See Section 11.1.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclock
clock frequency
-
450
MHz
tW
pulse width
CK, CK HIGH or LOW
1
-
ns
tACT
differential inputs active time
ns
tINACT
differential inputs inactive time
ns
tsu
setup time
DCS before CK
↑, CK↓, CSR HIGH; CSR
before CK
↑, CK↓, DCS HIGH
0.6
-
ns
DCS before CK
↑, CK↓, CSR LOW
0.5
-
ns
DODT, DCKE and data (Dn) before CK
↑,
CK
↓
0.5
-
ns
PAR_IN before CK
↑, CK↓
0.5
-
ns
th
hold time
DCS, DODT, DCKE and data (Dn) after
CK
↑, CK↓
0.4
-
ns
PAR_IN after CK
↑, CK↓
0.4
-
ns
Table 11.
Switching characteristics (667 mode, SELAB = HIGH)
At recommended operating conditions (see Table 8), unless otherwise specied. See Section 11.1.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fmax
maximum input clock frequency
450
-
MHz
tPDM
peak propagation delay
single bit switching;
from CK
↑ and CK↓ to Qn
[1] 1.2
-
1.8
ns
tPD
propagation delay
from CK
↑ and CK↓ to PPO
0.5
-
1.8
ns
tLH
LOW-to-HIGH delay
from CK
↑ and CK↓ to QERR
1.2
-
3
ns
tHL
HIGH-to-LOW delay
from CK
↑ and CK↓ to QERR
1
-
2.4
ns
tPDMSS
simultaneous switching peak
propagation delay
from CK
↑ and CK↓ to Qn
-
2.0
ns
tPHL
HIGH-to-LOW propagation delay
from RESET
↓ to Qn↓
--3
ns
from RESET
↓ to PPO↓
--3
ns
tPLH
LOW-to-HIGH propagation delay
from RESET
↓ to QERR↑
--3
ns
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