參數(shù)資料
型號(hào)： SSTUB32S868DHLFT
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 16/20頁(yè)
文件大小： 0K
描述： IC REGIST BUFF 25BIT DDR2 176BGA
產(chǎn)品變化通告： Product Discontinuation 09/Dec/2011
標(biāo)準(zhǔn)包裝： 1,000
邏輯類型： DDR2 的寄存緩沖器
電源電壓： 1.7 V ~ 1.9 V
位數(shù)： 25
安裝類型： 表面貼裝
封裝/外殼： 176-TFBGA
供應(yīng)商設(shè)備封裝： 176-CABGA（6x15）
包裝： 帶卷 (TR)
5
ICSSSTUB32S868D
Advance Information
08/14/06
The ICSSSTUB32S868D includes a parity checking function. Parity, which arrives one cycle after the data input to which
it applies, is checked on the PAR_IN input of the device. The corresponding QERR output signal for the data inputs
is generated two clock cycles after the data, to which the QERR signal applies, is registered. The ICSSSTUB32S868D
accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on
the DIMM-independent D-inputs (D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28 when
C = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is
even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined
with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state. If an
error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET
is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock
duration equal to the parity error duration or until RESET is driven low. If a parity error occurs on the clock cycle before
the device enters the low-power (LPM) and the QERR output is driven low, then it stays lateched low for the LPM duration
plus two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1,
DCS0 and DCS1) are not included in the parity check computation.
The C input controls the pinout configuration from register-A configuration (when low) to register-B configuration (when
high). The C input should not be switched during normal operation. It should be hardwired to a valid low or high level
to configure the register in the desired mode. The device also supports low-power active operation by monitoring both
system chip select (DCS0 and DCS1) and CSGEN inputs and will gate the Qn outputs from changing states when
CSGEN, DCS0, and DCS1 inputs are high. If CSGEN, DCS0 or DCS1 input is low, the Qn outputs will function normally.
Also, if both DCS0 and DCS1 inputs are high, the device will gate the QERR output from changing states. If either DCS0
or DCS1 is low, the QERR output will function normally. The RESET input has priority over the DCS0 and DCS1 control
and when driven low will force the Qn outputs low, and the QERR output high. If the chip-select control functionality
is not desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement for DCS0
and DCS1 would be the same as for the other D data inputs. To control the low-power mode with DCS0 and DCS1 only,
then the CSGEN input should be pulled up to VDD through a pullup resistor. The two VREF pins (A1 and V1) are
connected together internally by approximately 150 .. However, it is necessary to connect only one of the two VREF
pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor.
General Description (Continued)
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