參數(shù)資料
型號： SSTUA32866EC/G,551
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
封裝： 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96
文件頁數(shù)： 4/28頁
文件大?。?/td> 153K
代理商： SSTUA32866EC/G,551
SSTUA32866_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
12 of 28
NXP Semiconductors
SSTUA32866
1.8 V DDR2-667 congurable registered buffer with parity
[1]
This parameter is not necessarily production tested.
[2]
VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken
HIGH.
[3]
VREF, data and clock inputs must be held at valid levels (not oating) a minimum time of tINACT(max) after RESET is taken LOW.
[1]
Includes 350 ps of test-load transmission line delay.
[2]
This parameter is not necessarily production tested.
Table 8.
Timing requirements
At recommended operating conditions (see Table 6), unless otherwise specied. See Figure 2.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclock
clock frequency
-
450
MHz
tW
pulse width
CK, CK HIGH or LOW
1
-
ns
tACT
differential inputs active time
-
10
ns
tINACT
differential inputs inactive time
-
15
ns
tsu
set-up time
DCS before CK
↑, CK↓, CSR HIGH; CSR
before CK
↑, CK↓, DCS HIGH
0.7
-
ns
DCS before CK
↑, CK↓, CSR LOW
0.5
-
ns
DODT, DCKE and data (Dn) before CK
↑,
CK
↓
0.5
-
ns
PAR_IN before CK
↑, CK↓
0.5
-
ns
th
hold time
DCS, DODT, DCKE and data (Dn) after
CK
↑, CK↓
0.5
-
ns
PAR_IN after CK
↑, CK↓
0.5
-
ns
Table 9.
Switching characteristics
At recommended operating conditions (see Table 6), unless otherwise specied. See Section 11.1.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fmax
maximum input clock frequency
450
-
MHz
tPDM
peak propagation delay
single bit switching; from CK
↑
and CK
↓ to Qn
[1] 1.2
-
1.8
ns
tPD
propagation delay
from CK
↑ and CK↓ to PPO
0.5
-
1.8
ns
tLH
LOW-to-HIGH delay
from CK
↑ and CK↓ to QERR
1.2
-
3
ns
tHL
HIGH-to-LOW delay
from CK
↑ and CK↓ to QERR
1
-
2.4
ns
tPDMSS
simultaneous switching peak
propagation delay
from CK
↑ and CK↓ to Qn
-
2.0
ns
tPHL
HIGH-to-LOW propagation delay
from RESET
↓ to Qn↓
--3
ns
from RESET
↓ to PPO↓
--3
ns
tPLH
LOW-to-HIGH propagation delay
from RESET
↓ to QERR↑
--3
ns
Table 10.
Data output edge rates
At recommended operating conditions (see Table 6), unless otherwise specied. See Section 11.2.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
dV/dt_r
rising edge slew rate
from 20 % to 80 %
1
-
4
V/ns
dV/dt_f
falling edge slew rate
from 80 % to 20 %
1
-
4
V/ns
dV/dt_
absolute difference between dV/dt_r
and dV/dt_f
from 20 % or 80 %
to 80 % or 20 %
-
1
V/ns
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