參數(shù)資料
型號(hào): SSTUA32866EC/G,551
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 鎖存器
英文描述: 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
封裝: 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96
文件頁(yè)數(shù): 19/28頁(yè)
文件大?。?/td> 153K
代理商: SSTUA32866EC/G,551
SSTUA32866_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
26 of 28
NXP Semiconductors
SSTUA32866
1.8 V DDR2-667 congurable registered buffer with parity
15. Revision history
Table 14.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
SSTUA32866_2
20070326
Product data sheet
-
SSTUA32866_1
Modications:
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
3rd paragraph, 2nd sentence of Section 7 “Functional description”: changed “... and CK going
LOW.” to “... and CK going LOW.”
changed Parameter for VI to “input voltage”; moved “receiver” to Conditions
changed Parameter for VO to “output voltage”; moved “driver” to Conditions
changed Parameter for IO to “output current”; moved “continuous” to Conditions
Table 6 “Recommended operating conditions”: changed symbol “VTT” to “VT
Symbol IDD: changed Parameter to “supply current”; moved “static standby” and “static
operating” to Conditions
IDD, supply current, static standby: changed Max value from “100 A” to “2 mA”
Symbol IDDD: changed Parameter to “dynamic operating current per MHz”; moved “clock only”,
and “per each data input, 1 : 1 mode”, and “per each data input, 1 : 2 mode” to Conditions
Symbol Ci: changed Parameter to “input capacitance”; moved “data and CSR inputs”,
“CK and CK inputs”, and “RESET input” to Conditions
Table 8 “Timing requirements”, Symbol tW: changed Parameter to “pulse width”; moved “CK, CK
HIGH or LOW” to Conditions
changed Symbol “fMAX” to “fmax
changed Parameter for tPDM to “peak propagation delay”; moved “single bit switching” to
Conditions
changed Parameter for tPDMSS to “simultaneous switching peak propagation delay”
(throughout data sheet): changed “VDD/2” to “0.5VDD
SSTUA32866_1
(9397 750 14759)
20050715
Product data sheet
-
相關(guān)PDF資料
PDF描述
SSTUA32866EC/G,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUAF32866BHLFT 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
SSTUAF32869AHLFT 32869 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA150
SSTUB32864EC/G 32864 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUB32868ET/S 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176
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