參數(shù)資料
型號: SST89V516RD-33-I-PIE
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PDIP40
封裝: LEAD FREE, PLASTIC, MS-011AC, DIP-40
文件頁數(shù): 22/80頁
文件大小: 934K
代理商: SST89V516RD-33-I-PIE
Data Sheet
FlashFlex51 MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
29
2005 Silicon Storage Technology, Inc.
S71273-01-000
3/05
Symbol
Function
SPIE
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPE
SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1.4, P1.5, P1.6, P1.7.
DORD
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
MSTR
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
CPOL
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
CPHA
Clock Phase control bit. The CPHA bit with the CPOL bit control the clock and data
relationship between master and slave. See Figures 6-5 and 6-6.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
SPR1, SPR0
SPI Clock Rate Select bits. These two bits control the SCK rate of the device
configured as master. SPR1 and SPR0 have no effect on the slave. The relationship
between SCK and the oscillator frequency, fOSC, is as follows:
Symbol
Function
SPIF
SPI Interrupt Flag.
Upon completion of data transfer, this bit is set to 1.
If SPIE =1 and ES =1, an interrupt is then generated.
This bit is cleared by software.
WCOL
Write Collision Flag.
Set if the SPI data register is written to during data transfer.
This bit is cleared by software.
SPI Control Register (SPCR)
Location
76543210
Reset Value
D5H
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
00H
SPR1
SPR0
SCK = fOSC divided by
0
1
0
1
0
1
4
16
64
128
SPI Status Register (SPSR)
Location
76543210
Reset Value
AAH
SPIF
WCOL
------
00xxxxxxb
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