參數(shù)資料
型號(hào): SST89V516RD-33-I-PIE
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PDIP40
封裝: LEAD FREE, PLASTIC, MS-011AC, DIP-40
文件頁(yè)數(shù): 18/80頁(yè)
文件大?。?/td> 934K
代理商: SST89V516RD-33-I-PIE
Data Sheet
FlashFlex51 MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
25
2005 Silicon Storage Technology, Inc.
S71273-01-000
3/05
Symbol
Function
EXTRAM
Internal/External RAM access
0: Internal Expanded RAM access within range of 00H to 2FFH using MOVX @Ri /
@DPTR. Beyond 300H, the MCU always accesses external data memory.
For details, refer to Section 3.4, “Expanded Data RAM Addressing” .
1: External data memory access.
AO
Disable/Enable ALE
0: ALE is emitted at a constant rate of 1/3 the oscillator frequency in 6 clock mode, 1/6 fOSC in
12 clock mode.
1: ALE is active only during a MOVX or MOVC instruction.
Symbol
Function
GF2
General purpose user-defined flag.
DPS
DPTR registers select bit.
0: DPTR0 is selected.
1: DPTR1 is selected.
Symbol
Function
WDOUT
Watchdog output enable.
0: Watchdog reset will not be exported on Reset pin.
1: Watchdog reset if enabled by WDRE, will assert Reset pin for 32 clocks.
WDRE
Watchdog timer reset enable.
0: Disable watchdog timer reset.
1: Enable watchdog timer reset.
WDTS
Watchdog timer reset flag.
0: External hardware reset or power-on reset clears the flag.
Flag can also be cleared by writing a 1.
Flag survives if chip reset happened because of watchdog timer overflow.
1: Hardware sets the flag on watchdog overflow.
WDT
Watchdog timer refresh.
0: Hardware resets the bit when refresh is done.
1: Software sets the bit to force a watchdog timer refresh.
SWDT
Start watchdog timer.
0: Stop WDT.
1: Start WDT.
Auxiliary Register (AUXR)
Location
76543210
Reset Value
8EH
------
EXTRAM
AO
xxxxxx00b
Auxiliary Register 1 (AUXR1)
Location
76543210
Reset Value
A2H
----
GF2
0
-
DPS
xxxx00x0b
Watchdog Timer Control Register (WDTC)
Location
76543210
Reset Value
C0H
-
WDOUT
WDRE
WDTS
WDT
SWDT
xxx00000b
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