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參數(shù)資料
| 型號： | SST85LP1004B-M-C-LFTE |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PBGA91 |
| 封裝： | 14 X 24 MM, 1.30 MM HEIGHT, ROHS COMPLIANT, BGA-91 |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 910K |
| 代理商： | SST85LP1004B-M-C-LFTE |
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2010 Silicon Storage Technology, Inc.
S71420-01-000
04/10
4
4 GByte NANDrive
SST85LP1004B
Advance Information
Error Correction Code (ECC)
High performance is achieved through optimized hardware error detection and correction.
Internal Direct Memory Access (DMA)
The NANDrive uses internal DMA allowing instant data transfer from buffer to flash media. This imple-
mentation eliminates microcontroller overhead associated with the traditional, firmware-based
approach, thereby increasing the data transfer rate.
NAND Flash
The NANDrive family utilize standard NAND Flash for data storage. Because the re-flow process can
alter the NANDrive content, do not program the SST85LP1004B NAND before the reflow process.
Advanced NAND Management Technology
Advanced NAND management technology balances the wear on erased blocks with an advanced
wear-leveling scheme which provides a minimum of 7 million host write cycles. Advanced NAND man-
agement technology tracks the number of program/erase cycles within a group. When the host
updates data, higher priority is given to the less frequently written erase blocks; thereby, evenly distrib-
uting host writes within a wear-leveling group.
The product also supports a global wear-leveling feature which can be enabled or disabled by the Host
command. When the global wear-leveling is enabled, the wear-leveling is performed both across and
within the groups. Please contact SST for more information about this feature. By default, global wear-
leveling is enabled.
Advanced NAND management technology enhances NANDrive security with password protection and
four independent protection zones which can be set to Read-only or Hidden.
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