參數(shù)資料
型號： SST55VD020-60-I-TQWE
元件分類： 存儲控制器/管理單元
英文描述： IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PQFP100
封裝： 14 X 14 MM, ROHS COMPLIANT, MS-026, TQFP-100
文件頁數(shù)： 9/45頁
文件大?。?/td> 666K
代理商： SST55VD020-60-I-TQWE
Data Sheet
NAND Controller
SST55VD020
2009 Silicon Storage Technology, Inc.
S71355-03-000
07/09
17
Feature Register (Write Only)
This register provides additional command-specific parameters to the NAND Controller.
Sector Count Register
This register contains the numbers of sectors of data requested to be transferred on a Read or Write operation between the
host and the NAND Controller. If the value in this register is zero, a count of 256 sectors is specified. If the command was
successful, this register is zero at command completion. If not successfully completed, the register contains the number of
sectors that need to be transferred in order to complete the request.
Sector Number (LBA 7-0) Register
This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any NAND Controller data
access for the subsequent command.
Cylinder Low (LBA 15-8) Register
This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block Address.
Cylinder High (LBA 23-16) Register
This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address.
Drive/Head (LBA 27-24) Register
The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/
head/sector addressing. The bits are defined as follows:
Symbol
Function
LBA
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address mode (LBA).
When LBA=0, Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is
selected. In Logical Block mode, the Logical Block Address is interpreted as follows:
LBA7-LBA0: Sector Number register D7-D0.
LBA15-LBA8: Cylinder Low register D7-D0.
LBA23-LBA16: Cylinder High register D7-D0.
LBA27-LBA24: Drive/Head register bits HS3-HS0.
DRV
DRV is the drive number. When DRV=0 (Master), Master is selected.
When DRV=1 (Slave), Slave is selected.
HS3
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number.
It is Bit 27 in the Logical Block Address mode.
HS2
When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number.
It is Bit 26 in the Logical Block Address mode.
HS1
When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number.
It is Bit 25 in the Logical Block Address mode.
HS0
When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number.
It is Bit 24 in the Logical Block Address mode.
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value
1LBA
1
DRV
HS3
HS2
HS1
HS0
1010 0000b
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