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參數(shù)資料
| 型號： | SPLC782A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16COM/40SEG Controller/Driver |
| 中文描述： | 16COM/40SEG控制器/驅(qū)動器 |
| 文件頁數(shù)： | 5/40頁 |
| 文件大?。?/td> | 1670K |
| 代理商： | SPLC782A |
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SPLC782A
4. SIGNAL DESCRIPTIONS
Sunplus Technology Co., Ltd.
Proprietary & Confidential
5
FEB. 15, 2005
Version: 1.7
Mnemonic
PIN No.
Type
Description
VDD
19, 20, 28
I
Logic Power input
VSS
11, 12, 37
I
Ground
VPP
23, 24
I
LCD Voltage; V
LCD
= VPP - VSS
V2
V3
22
21
I
LCD Bias Voltage Control.
Open for 1/5 Bias, Short for 1/4 Bias
E
27
I
It is a start signal to read data or write data.
R / W
26
I
It is a signal to select read or write.
1: Read, 0: Write.
RS
25
I
It is a signal to select register.
1: Data register (for read and write)
0: Instruction register (for write),
Busy flag -- address counter (for read).
DB3 - DB0
32 - 29
I/O
Low-order 4 data bits
DB7 - DB4
36 - 33
I/O
High-order 4 data bits
SEG80 - SEG1
46 - 125
O
Segment signals for LCD.
COM16 - COM9
45 - 38
O
Common signals for LCD.
COM8 - COM1
1 - 8
O
Common signals for LCD.
TYPE
14
I
LCD Alternate Signals.
TYPE = 0: Type-A
TYPE = 1: Type-B
DIRC
15
I
Common Scan Direction
DIRC = 0: COM1
COM2
…
COM15
COM16
DIRC = 1: COM16
COM15
…
COM2
COM1
SHL
16
I
Segment Shift Direction
SHL = 0: SEG1
SEG2
…
SEG79
SEG80
SHL = 1: SEG80
SEG79
…
SEG2
SEG1
MOD1
MOD0
18
17
I
CGROM / CGRAM Mode Select
MOD1
MOD0
Function
1
1
1
1
0
0
0
0
$00 - $0F as CGRAM
$00 - $07 as CGRAM, $08 - $0F as CGROM
$00 - $03 as CGRAM, $04 - $0F as CGROM
$00 - $0F as CGROM
OSC1
13
For internal clock operation, leave this pin open.
For external clock operation, the clock is input to OSC1.
CL2
10
O
Test Mode Clock Output; Open for normally use.
D
9
O
Test Mode Data Output; Open for normally use.
SunpusConidenia
Fo PARTMNERUseOny
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