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參數(shù)資料
| 型號： | SPL505YC264BT |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 封裝： | 6 X 17 MM, LEAD FREE, MO-153, TSSOP-64 |
| 文件頁數(shù)： | 5/27頁 |
| 文件大?。?/td> | 314K |
| 代理商： | SPL505YC264BT |
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SPL505YC264BT
Rev 1.4 May 21, 2007
Page 13 of 27
Byte 18 Control Register 18
The SPL505YC264BT requires a parallel resonance crystal.
Substituting
a
series
resonance
crystal
causes
the
SPL505YC264BT to operate at the wrong frequency and
violate the ppm specification. For most applications there is a
300-ppm frequency shift between series and parallel crystals
due to incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal sees must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. The common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal is
not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Bit
@Pup
Name
Description
7
0
PCIF/PCI_DSC2
Drive Strength Control - DSC[2:0]
6
1
PCIF/PCI_DSC0
5
0
USB_DSC2
4
0
USB_DSC0
3
0
SE1/SE2_DSC2
2
0
SE1/SE2_DSC0
1
0
REF_DSC2
0
REF_DSC0
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
DSC_2
(Byte18)
DSC_1
(Vario us B ytes)
DSC_0
(Byte 18)
Buf f er
Strength
1
Strongest
1
0
1
0
1
0
Def ault PCI
0
1
Def ault REF/Usb
0
1
0
1
0
Weakest
Figure 1. Crystal Capacitive Clarification
XTAL
Ce2
Ce1
Cs1
Cs2
X 1
X 2
Ci1
Ci2
C lock C hip
Trace
2.8 pF
Trim
33 pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SPL505YC264BTT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 CK505 v0.85 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SPL5100PT | 制造商:CHENMKO 制造商全稱:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SPL520LLPT | 制造商:CHENMKO 制造商全稱:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER RECTIFIER |
| SPL53-1024 | 制造商:Power-One 功能描述: |
| SPL53-4000 | 制造商:Power-One 功能描述: |
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