參數(shù)資料
型號(hào): SPL505YC264BT
廠商: SILICON LABORATORIES
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64
封裝: 6 X 17 MM, LEAD FREE, MO-153, TSSOP-64
文件頁數(shù): 26/27頁
文件大小: 314K
代理商: SPL505YC264BT
SPL505YC264BT
Rev 1.4 May 21, 2007
Page 8 of 27
2
1
PCI2_OE
Output enable for PCI2, 0 = Output Disabled, 1 = Output Enabled
1
PCI1_OE
Output enable for PCI1, 0 = Output Disabled, 1 = Output Enabled
0
1
PCI0_OE
Output enable for PCI0, 0 = Output Disabled, 1 = Output Enabled
Byte 2: Control Register 2 (continued)
Bit
@Pup
Name
Description
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
1
SRC11_OE
Output enable for SRC11, 0 = Output Disabled, 1 = Output Enabled
6
1
SRC10_OE
Output enable for SRC10, 0 = Output Disabled, 1 = Output Enabled
5
1
SRC9_OE
Output enable for SRC9, 0 = Output Disabled, 1 = Output Enabled
4
1
SRC8/ITP_OE
Output enable for SRC8 or ITP, 0 = Output Disabled, 1 = Output Enabled
3
1
SRC7_OE
Output enable for SRC7, 0 = Output Disabled, 1 = Output Enabled
2
1
SRC6_OE
Output enable for SRC6, 0 = Output Disabled, 1 = Output Enabled
1
SRC5_OE
Output enable for SRC5, 0 = Output Disabled, 1 = Output Enabled
0
1
SRC4_OE
Output enable for SRC4, 0 = Output Disabled, 1 = Output Enabled
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
1
SRC3_OE
Output enable for SRC3, 0 = Output Disabled, 1 = Output Enabled
6
1
SRC2/SATA_OE
Output enable for SATA/SRC2, 0 = Output Disabled, 1 = Output Enabled
5
1
SRC1_OE
Output enable for SRC, 0 = Output Disabled, 1 = Output Enabled
4
1
SRC0/DOT96_OE
Output enable for SRC0/DOT96
0 = Output Disabled, 1 = Output Enabled
3
1
CPU1_OE
Output enable for CPU1, 0 = Output Disabled, 1 = Output Enabled
2
1
CPU0_OE
Output enable for CPU0, 0 = Output Disabled, 1 = Output Enabled
1
PLL1_SS_EN
Enable PLL1’s spread modulation,
0 = Spread Disabled 1 = Spread Enabled
0
1
PLL3_SS_EN
Enable PLL3’s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
OE#_0/2_EN_A
Enable OE#_0/2 (clk req)
0 = Disabled OE#_0/2, 1 = Enabled OE#_0/2,
6
0
OE#_0/2_SEL_A
Set OE#_0/2 → SRC0 or SRC2
0 = OE#_0/2→SRC0, 1 = OE#_0/2→SRC2
5
0
OE#_1/4_EN_A
Enable OE#_1/4 (clk req)
0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4,
4
0
OE#_1/4_SEL_A
Set OE#_1/4 → SRC1 or SRC4
0 = OE#_1/4→SRC1, 1 = OE#_1/4→SRC4
3
0
OE#_0/2_EN_B
Enable OE#_0/2 (clk req)
0 = Disabled OE#_0/2 1 = Enabled OE#_0/2
2
0
OE#_0/2_SEL_B
Set OE#_0/2 → SRC0 or SRC2
0 = OE#_0/2→SRC0, 1 = OE#_0/2→SRC2
1
0
OE#_1/4_EN_B
Enable OE#_1/4 (clk req)
0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4,
0
OE#_1/4_SEL_B
Set OE#_1/4 → SRC1 or SRC4
0 = OE#_1/4→SRC1, 1 = OE#_1/4→SRC4
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