參數(shù)資料
型號: SPEAR300-2
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 333 MHz, RISC MICROCONTROLLER, PBGA289
封裝: 15 X 15 MM, 1.70 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, LFBGA-289
文件頁數(shù): 73/83頁
文件大?。?/td> 1027K
代理商: SPEAR300-2
SPEAr300
Timing requirements
Doc ID 16324 Rev 2
75/83
6.7
SSP timing characteristics
This module provides a programmable length shift register which allows serial
communication with other SSP devices through a 3 or 4 wire interface (SSP_CLK,
SSP_MISO, SSP_MOSI and SSP_CSn). The SSP supports the following features:
Master/Slave mode operations
Chip-selects for interfacing to multiple slave SPI devices.
3 or 4 wire interface (SSP_SCK, SSP_MISO, SSP_MOSI and SSP_CSn)
Single interrupt
Separate DMA events for SPI Receive and Transmit
16-bit shift register
Receive buffer register
Programmable character length (2 to 16 bits)
Programmable SSP clock frequency range
8-bit clock pre-scaler
Programmable clock phase (delay or no delay)
Programmable clock polarity
Note:
The following tables and figures show the characterization of the SSP using the SPI
protocol.
T = Tc(CLK) = SSP_CLK period is equal to the SSP module master clock divided by a
configurable divider.
Figure 42.
SSP_CLK timings
Table 44.
Timing requirements for SSP (all modes)
No.
Parameters
Value
Unit
1Tc(CLK)
Cycle time, SSP_CLK
24
ns
2Tw(CLKH)
Pulse duration, SSP_CLK high
0.49T - 0.51T
ns
3Tw(CLKL)
Pulse duration, SSP_CLK low
0.51T - 0.49T
ns
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