參數(shù)資料
型號: SPEAR300-2
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 333 MHz, RISC MICROCONTROLLER, PBGA289
封裝: 15 X 15 MM, 1.70 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, LFBGA-289
文件頁數(shù): 4/83頁
文件大?。?/td> 1027K
代理商: SPEAR300-2
Architecture overview
SPEAr300
12/83
Doc ID 16324 Rev 2
2.2
System controller
The System Controller provides an interface for controlling the operation of the overall
system.
Main features:
Power saving system mode control
Crystal oscillator and PLL control
Configuration of system response to interrupts
Reset status capture and soft reset generation
Watchdog and timer module clock enable
Remap control
General purpose peripheral control r
System and peripheral clock control and status
2.2.1
Clock and reset system
The clock system is a fully programmable block that generates all the clocks for the
SPEAr300.
The default operating clock frequencies are:
CPU_CLK @ 333 MHz for the CPU.
HCLK @ 166 MHz for AHB bus and AHB peripherals.
PCLK @ 83 MHz for, APB bus and APB peripherals.
DDR_CLK @ 100-333 MHz for DDR memory interface.
The above frequencies are the maximum allowed values. The clock frequencies can be
modified by programming the clock system registers.
The clock system consists of 2 main parts: a multi clock generator block and two internal
PLLs.
相關PDF資料
PDF描述
SPL505YC264ATT PROC SPECIFIC CLOCK GENERATOR, PDSO64
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SPL505YC264BT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64
SPW08F0D SINGLE COLOR LED, PURE WHITE, 3.5 mm
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