
SPC560P50x, SPC560P44x
For high priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the interrupt service routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR needs to be executed. It also provides an ample number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the resource can not preempt each other.
The INTC provides the following features:
●
Unique 9-bit vector for each separate interrupt source
●
8 software triggerable interrupt sources
●
16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source
●
Ability to modify the ISR or task priority.
–
Modifying the priority can be used to implement the Priority Ceiling Protocol for
accessing shared resources.
●
Two external high priority interrupts directly accessing the main core and IOP critical
interrupt mechanism
3.3.7
System clocks and clock generation
The following list summarizes the system clock and clock generation on the SPC560Px:
●
Lock detect circuitry continuously monitors lock status
●
Loss of clock (LOC) detection for PLL outputs
●
Programmable output clock divider (
÷1, ÷2, ÷4, ÷8)
●
FlexPWM module and eTimer module can run on an independent clock source
●
On-chip oscillator with automatic level control (tbc)
●
Internal 16-MHz RC-Oscillator for rapid start-up and safe mode
–
Supports frequency trimming by user application
3.3.8
Frequency modulated PLL (FMPLL)
The FMPLL allows the user to generate high speed system clocks from an 4MHz to 40MHz
input clock. Further, the FMPLL supports programmable frequency modulation of the
system clock. The PLL multiplication factor, output clock divider ratio are all software
configurable.
The PLL has the following major features:
●
Input clock frequency from an 4MHz to 40MHz
●
Voltage controlled oscillator (VCO) range from 256MHz to 512MHz
●
Reduced frequency divider (RFD) for reduced frequency operation without forcing the
PLL to relock
●
Frequency modulated PLL
–
Modulation enabled/disabled through software