
SPC560P50x, SPC560P44x
–
Triggered mode only
–
Four independent result queues (1x16 entries, 2x8 entries, 1x4 entries)
–
Result alignment circuitry (left justified; right justified)
–
32-bit read mode allows to have channel ID on one of the 16-bit part
–
DMA compatible interfaces
3.3.26
Cross Triggering Unit (CTU)
The Cross Triggering Unit (CTU) allows automatic generation of ADC conversion requests
on user selected conditions without CPU load during the PWM period and with minimized
CPU load for dynamic configuration.
It implements the following features:
●
Double buffered trigger generation unit with up to eight independent triggers generated
from external triggers
●
Trigger generation unit configurable in sequential mode or in triggered mode
●
Each Trigger can be appropriately delayed to compensate the delay of external low
pass filter
●
Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation
●
Double buffered ADC command list pointers to minimize ADC-trigger unit update
●
Double buffered ADC conversion command list with up to 24 ADC commands
●
Each trigger has the capability to generate consecutive commands
●
ADC conversion command allows to control ADC channel from each ADC, single or
synchronous sampling, independent result queue selection
3.3.27
Junction temperature sensor
The SPC560Px has a junction temperature sensor to allow to measure, by the ADC, the
temperature of the silicon.
These are the key parameters of the junction temperature sensor:
●
Nominal temperature range from -40°C to +150°C
●
Accuracy of the sensor +/- 5°C (tbc)
3.3.28
Nexus Development Interface (NDI)
The NDI (Nexus Debug Interface) block provides real-time development support capabilities
for the SPC560Px Power Architecture based MCU in compliance with the IEEE-ISTO 5001-
2003 standard. This development support is supplied for MCUs without requiring external
address and data pins for internal visibility. The NDI block is an integration of several
individual Nexus blocks that are selected to provide the development support interface for
this device. The NDI block interfaces to the host processor and internal busses to provide
development support as per the IEEE-ISTO 5001-2003 Class 2+ standard. The
development support provided includes access to the MCUs internal memory map and
access to the processors internal registers during run time.
The Nexus Interface provides the following features:
●
Configured via the IEEE 1149.1
●
All Nexus port pins operate at VDDIO (no dedicated power supply)