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參數(shù)資料
| 型號： | SPC560P50L3CEFA |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封裝： | ROHS COMPLIANT, LQFP-100 |
| 文件頁數(shù)： | 25/26頁 |
| 文件大?。?/td> | 509K |
| 代理商： | SPC560P50L3CEFA |
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SPC560P50x, SPC560P44x
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100-pin package: 51 general-purpose pins supporting input/output operations plus
16 general-purpose pins supporting input operations (67 in total). Out of these 67
pins, 25 have external interrupt capability.
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NDI - Nexus development interface per IEEE-ISTO 5001-2003 standard Class 2+
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IEEE 1149.7 class 4 (narrow pin interface) to allow optimized device I/O count
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Backward compatible to JTAG (IEEE 1149.1)
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JTAG (IEEE 1149.1) 4 pin interface
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VREG - Voltage regulator for regulation into 3.3V input down to 1.2V nominal core logic
level with external transistor
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Embedded junction temperature sensor
3.3
Feature details
3.3.1
High performance e200z0 core processor
The e200z0 Power ArchitectureTM core provides the following features:
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High performance e200z0 core processor for managing peripherals and interrupts
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Single issue 4-stage pipeline in-order execution 32-bit Power ArchitectureTM CPU
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Harvard architecture
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Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
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Results in smaller code size footprint
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Minimizes impact on performance
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Branch processing acceleration using lookahead instruction buffer
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Load/store unit
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1-cycle load latency
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Misaligned access support
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No load-to-use pipeline bubbles
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Thirty-two 32-bit general purpose registers (GPRs)
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Separate instruction bus and load/store bus Harvard architecture
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Hardware vectored interrupt support
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Reservation instructions for implementing read-modify-write constructs
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Long cycle time instructions, except for guarded loads, do not increase interrupt latency
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Extensive system development support through Nexus debug port
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Non maskable Interrupt support
3.3.2
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between 4 master
ports and 3 slave ports. The crossbar supports a 32-bit address bus width and a 32-bit data
bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any
slave port; but one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic will select the higher priority master and grant it ownership of the slave port.
All other masters requesting that slave port will be stalled until the higher priority master
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| SPC560P50L5CEFB | MICROCONTROLLER, PQFP144 |
| SPC5668EF1AVMG | 32-BIT, FLASH, 116 MHz, MICROCONTROLLER, PBGA208 |
| SPC5668GF1AVMG | 32-BIT, FLASH, 116 MHz, MICROCONTROLLER, PBGA208 |
| SPC5668GF0AVMG | 32-BIT, FLASH, 116 MHz, MICROCONTROLLER, PBGA208 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPC560P50L3CEFAR | 功能描述:32位微控制器 - MCU 32-BIT Embedded MCU 64 MHz, 5V 512kB RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| SPC560P50L3CEFAY | 制造商:STMicroelectronics 功能描述:MID MICROCONTROLLER - Trays |
| SPC560P50L3CEFBR | 制造商:STMicroelectronics 功能描述:IC MCU 32BIT 512KB FLASH 100LQFP |
| SPC560P50L5BEFAR | 制造商:STMicroelectronics 功能描述:MID MICROCONTROLLER - Tape and Reel |
| SPC560P50L5BEFAY | 制造商:STMicroelectronics 功能描述:MID MICROCONTROLLER - Trays |
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