參數(shù)資料
型號: SPC5200CVR400BR2
廠商: Freescale Semiconductor
文件頁數(shù): 71/72頁
文件大小: 0K
描述: IC MPU 32BIT 400MHZ 272-PBGA
標準包裝: 500
系列: MPC52xx
處理器類型: 32-位 MPC52xx PowerPC
速度: 400MHz
電壓: 1.5V
安裝類型: 表面貼裝
封裝/外殼: 272-BBGA
供應(yīng)商設(shè)備封裝: 272-PBGA(27x27)
包裝: 帶卷 (TR)
MPC5200B Data Sheet, Rev. 4
8
Freescale Semiconductor
Table 6. Power Dissipation
Core Power Supply (VDD_CORE)
SpecID
Mode
SYS_XTAL/XLB/PCI/IPB/CORE (MHz)
Unit
Notes
33/66/33/33/264
33/132/66/132/396
Typ
Operational
727.5
1080
mW
(1),(2)
1 Typical core power is measured at VDD_CORE = 1.5 V, Tj = 25 °C
2 Operational power is measured while running an entirely cache-resident program with floating-point multiplication
instructions in parallel with a continuous PCI transaction via BestComm.
D5.1
Doze
600
mW
3 Doze power is measured with the e300 core in Doze mode, the system oscillator, System PLL and Core PLL are
active, all other system modules are inactive
D5.2
Nap
225
mW
4 Nap power is measured with the e300 core in Nap mode, the system oscillator, System PLL and Core PLL are
active, all other system modules are inactive
D5.3
Sleep
225
mW
5 Sleep power is measured with the e300 core in Sleep mode, the system oscillator, System PLL and Core PLL are
active, all other system modules are inactive
D5.4
Deep-Sleep
52.5
mW
6
Deep-Sleep power is measured with the e300 core in Sleep mode, the system oscillator, System PLL, Core
PLL and all other system modules are inactive
D5.5
PLL Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)
Mode
Typ
Unit
Notes
Typical
2
mW
(7)
7 Typical PLL power is measured at SYS_PLL_AVDD = CORE_PLL_AVDD = 1.5 V, Tj = 25 °C
D5.6
Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO8)
8 IO power figures given in the table represent the worst case scenario. For the VDD_MEM_IO rail connected to
2.5 V the IO power is expected to be lower and bounded by the worst case with VDD_MEM_IO connected to 3.3 V.
Mode
Typ
Unit
Notes
Typical
33
mW
(9)
9 Unloaded typical I/O power is measured in Deep-Sleep mode at VDD_IO = VDD_MEM_IO
SDR= 3.3 V, Tj = 25 °C
D5.7
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