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參數(shù)資料
| 型號(hào)： | SPAKXC16Z1CFC25 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 25 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, SMT-132 |
| 文件頁數(shù)： | 62/200頁 |
| 文件大?。?/td> | 1383K |
| 代理商： | SPAKXC16Z1CFC25 |
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MOTOROLA
M68HC16ZEC20/D
10
NOTES:
1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.
2. The base configuration of the MC68HC16Z1 requires a 32.768 kHz crystal reference, and the base con-
figuration of the M68HC16Z2 requires a 4.194 MHz crystal reference. Both devices can be ordered with
either crystal reference as a mask option.
3. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The mini-
mum allowable tXcyc period is reduced when the duty cycle of the external clock varies. The relationship
between external clock input duty cycle and minimum tXcyc is expressed:
Minimum tXcyc period = minimum tXCHL / (50% – external clock input duty cycle tolerance).
4. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low
during reset). Does not pertain to an external reference applied while the PLL is enabled (MODCLK pin
held high during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of
the reference signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are
not critical.
5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the
relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and
DS to fall outside the limits shown in specification 9.
6. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the nega-
tion of a heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated
specification between multiple chip selects does not apply to chip selects being used for synchronous
ECLK cycles.
7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT
on fast cycle reads. The user is free to use either hold time.
8. Maximum value is equal to (tcyc / 2) + 25 ns.
9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data
setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ig-
nored. The data must only satisfy the data-in to clock low setup time (specification 27) for the following
clock cycle. BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the
following clock cycle.
10. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all
cycles of the current operand transfer are complete.
11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time
(specification 47A).
12. After external RESET negation is detected, a short transition period (approximately 2) tcyc elapses, then
the SIM drives RESET low for 512 tcyc.
13. External assertion of the RESET input can overlap internally-generated resets. To insure that an exter-
nal reset is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
14. External logic must pull RESET high during this period in order for normal MCU operation to begin.
15. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases.
16.Address access time = (2.5 + WS) tcyc – tCHAV – tDICL
Chip select access time = (2 + WS) tcyc – tCLSA – tDICL
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
100
CLKOUT High to Phase 1 Asserted15
tCHP1A
340
ns
101
CLKOUT High to Phase 2 Asserted15
tCHP2A
340
ns
102
Phase 1 Valid to AS or DS Asserted15
tP1VSA
10
—
ns
103
Phase 2 Valid to AS or DS Asserted15
tP2VSN
10
—
ns
104
AS or DS Valid to Phase 1 Negated15
tSAP1N
10
—
ns
105
AS or DS Negated to Phase 2 Negated15
tSNP2N
10
—
ns
Table A–6 AC Timing (Continued)
(V
DD
and V
DDSYN
= 5.0 Vdc
± 5%, V
SS
= 0 Vdc, T
A
= T
L
to T
H)
1
Num
Characteristic
Symbol
Min
Max
Unit
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