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| 型號： | SP506CM-L |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 15/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX WAN MULTI-MODE 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 7/7 |
| 規(guī)程： | 多協(xié)議 |
| 電源電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1441 SP506CM-L-ND |
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Exar Coporation 48720 Kato Road, Fremont CA, 94538 (50) 668-7000 Fax (50) 668-707 www.exar.com
SP506_0_0870
Receiver Enable and Output
Only one receiver includes an enable line.
The SCTEN input for the SCT receiver can
enable or tri-state the output of the receiver.
When the pin is at a logic "0", the receiver
output is high impedance and any input
termination internal connected is switched
off. The inputs will be at approximately 0k
during tri-state.
All receivers include a fail-safe feature that
outputs a logic "" when the receiver inputs
areopen. Thedifferentialreceiversallocated
for data and clock signals (RxD, RxC, and
SCT) have advanced fail-safe that outputs
a logic "" when the inputs are either open,
shorted, or terminated. Other discrete or
integrated implementations require external
pull-up and pull-down resistors to define the
receiver output state. For single-ended V.28
receivers, there are internal 5k pull-down
resistors on the inputs which produces a
logic high ("") at the receiver outputs. The
single-ended V.0 receivers produce a logic
LOW ("0") on the output when the inputs are
open. Thisisduetoaninternalpull-updevice
connected to the input. The differential re-
ceivershavethesameinternalpull-updevice
on the non-inverting input which produces
a logic HIGH ("") at the receiver output,
representing an "OFF" state to the HDLC
controller. The three differential receivers
when configured in V.35 mode (RxD, RxC
& SCT) will also include fail-safe even when
the internal termination resistor network is
connected and the inputs are either shorted
or floating.
Decoder
The SP506 has the ability to change the
interface mode of the drivers or receivers
via a 4–bit switch. The decoder for the driv-
ers and receivers can be latched through a
control pin.
The control word can be latched either high
or low to write the appropriate code into the
SP506. The codes shown in Tables and
2 are the only specified, valid modes for the
SP506. Undefined codes may represent
other interface modes not specified (consult
the factory for more information).The drivers
and receivers are controlled with the data
bits labeled DEC
3–DEC0. All of the drivers
outputs and receiver outputs can be put
into tri-state mode by writing 0000 to the
driver decode switch. All internal termination
networks are switched off during this mode.
Individual tri-state capability is possible for
all drivers through each driver's own enable
controlinput. TheSCTreceiveralsocontains
an individual enable input. When this control
pin is disabled (logic "0"), the V. and V.35
input termination is deactivated. The 0000
decoderwordwilloverridetheenablecontrol
line for the one receiver (SCT).
The SP506 contains internal loopback ca-
pabilities for self-diagnostic tests. Loopback
is enabled through the decoder. To initiate
single-ended mode loopback, the decoder
word is 00. To initiate differential mode
loopback, the decoder word is 0. The
minimum transmission rates into the SP506
under loopback conditions are 20kbps for
single-endedmodeand5Mbpsfordifferential
mode. The driver outputs are tri-stated and
the receiver inputs are disabled during loop-
back. The receiver input impedance during
loopback is approximately 0k.
The SP506 is equipped with a latch control
forthefour(4)decoderbits. Thelatchcontrol
pin is pin 8 of the SP506. The latch control
is active low, a logic low on pin 8 will latch
the decoder signals. A logic "" on pin 8 will
force the latch to be transparent to the user.
A pulse width of at least 30ns is required to
latch the decoder for the next mode. The
resultant output is typically 600ns after the
latch control pin is toggled assuming that
the decoder word is set.
NET1/2 & TBR2 European Compliancy
As with all of Exar's previous multi-proto-
col serial transceiver ICs, the drivers and
receivers have been designed to meet all
the requirements to NET/2. The SP506 is
internally tested to all the NET/2 physical
layer testing parameters and the ITU Series
V specifications.
WiththeemergenceofETSITBR2(Technical
BasisforRegulation)documentnow in place
as an alternative for European compliancy,
Exar has tested the SP506 to TBR2 speci-
fications to ensure "CE" approval for either
testing method.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SP506CM-L | 制造商:Exar Corporation 功能描述:IC WAN MULTIMODE SER TXRX 5.25V LQFP80 |
| SP506EB | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Multi-Protocol Serial Transceivers |
| SP506EK | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Multi-Protocol Serial Transceivers |
| SP506RB | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:Multi-Protocol Serial Transceivers |
| SP507 | 制造商:SIPEX 制造商全稱:Sipex Corporation 功能描述:+5V, Single Chip WAN Multi-Mode Serial Transceiver |
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