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參數(shù)資料
| 型號(hào)： | SNJ54BCT8245AJT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 總線收發(fā)器 |
| 英文描述： | BCT/FBT SERIES, 8-BIT BOUNDARY SCAN TRANSCEIVER, TRUE OUTPUT, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁(yè)數(shù)： | 5/30頁(yè) |
| 文件大?。?/td> | 630K |
| 代理商： | SNJ54BCT8245AJT |
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SN54BCT8245A, SN74BCT8245A
SCAN TEST DEVICES
WITH OCTAL BUS TRANSCEIVERS
SCBS043E MAY 1990 REVISED JULY 1996
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
parallel-signature analysis (PSA)
Data appearing at the device input terminals is compressed into a 16-bit parallel signature in the shift-register
elements of the BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the input
BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow latches of the output BSCs
remains constant and is applied to the device outputs. Figure 6 illustrates the 16-bit linear-feedback
shift-register algorithm through which the signature is generated. An initial seed value should be scanned into
the BSR before performing this operation.
=
I1
O1
I2
I3
I4
I5
I6
I7
I8
O2
O3
O4
O5
O6
O7
O8
=
Figure 6. 16-Bit PSA Configuration
simultaneous PSA and PRPG (PSA / PRPG)
Data appearing at the device input terminals is compressed into an 8-bit parallel signature in the shift-register
elements of the input BSCs on each rising edge of TCK. This data is then updated in the shadow latches of the
input BSCs and applied to the inputs of the normal on-chip logic. At the same time, an 8-bit pseudo-random
pattern is generated in the shift-register elements of the output BSCs on each rising edge of TCK, updated in
the shadow latches, and applied to the device output terminals on each falling edge of TCK. Figure 7 illustrates
the 8-bit linear-feedback shift-register algorithm through which the signature and patterns are generated. An
initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes
will not produce additional patterns.
=
I1
O1
I2
I3
I4
I5
I6
I7
I8
O2
O3
O4
O5
O6
O7
O8
=
Figure 7. 8-Bit PSA / PRPG Configuration
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