參數(shù)資料
型號(hào)： SN74LVTH18504APM
廠商： TEXAS INSTRUMENTS INC
元件分類： 總線收發(fā)器
英文描述： LVT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64
封裝： PLASTIC, QFP-64
文件頁(yè)數(shù)： 7/40頁(yè)
文件大小： 594K
代理商： SN74LVTH18504APM
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2
→ BIT 0
MSB
→ LSB
DESCRIPTION
X00
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/40-bit mode (PRPG)
X10
Parallel-signature analysis /40-bit mode (PSA)
011
Simultaneous PSA and PRPG /20-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up /20-bit mode (PSA/COUNT)
While the control input BSCs (bits 47–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 47–46 of the BSR) control the drive state (active or high impedance) of the selected
device output pins. These BCR instructions are only valid when the device is operating in one direction of data
flow (that is, OEAB
≠ OEBA). Otherwise, the bypass instruction is operated.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the
associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode
BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated
device I/O pins on each falling edge of TCK.
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