- 您現在的位置：買賣IC網 > PDF目錄98089 > SN74LVTH18504APM (TEXAS INSTRUMENTS INC) LVT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 PDF資料下載
參數資料
| 型號： | SN74LVTH18504APM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數： | 38/40頁 |
| 文件大?。?/td> | 594K |
| 代理商： | SN74LVTH18504APM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當前第38頁第39頁第40頁
SN54LVTH18504A, SN54LVTH182504A, SN74LVTH18504A, SN74LVTH182504A
3.3-V ABT SCAN TEST DEVICES
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS667B – JULY 1996 – REVISED JUNE 1997
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
state diagram description
The TAP controller is a synchronous finite-state machine that provides test control signals throughout the
device. The state diagram shown in Figure 1 is in accordance with IEEE Std 1149.1-1990. The TAP controller
proceeds through its states, based on the level of TMS at the rising edge of TCK.
As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is defined as a state the TAP controller can retain for
consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register at a time can be accessed.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the ’LVTH18504A and ’LVTH182504A, the instruction register is reset to the binary value 10000001, which
selects the IDCODE instruction. Bits 47–46 in the boundary-scan register are reset to logic 1, ensuring that
these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked,
the outputs would be at high-impedance state). Reset values of other bits in the boundary-scan register should
be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the
PSA test operation.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
相關PDF資料 |
PDF描述 |
|---|---|
| SN54LVTH2952FK | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQCC28 |
| SN54LVTH543W | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP24 |
| SN74LVTH543DGV | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| SN54LVTH573J | LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| SN54LVTH573FK | LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SN74LVTH18504APMG4 | 功能描述:特定功能邏輯 3.3-V ABT w/20-Bit Univ Bus Transceiver RoHS:否 制造商:Texas Instruments 產品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVTH18504APMR | 功能描述:特定功能邏輯 10-Bit Bus/MOS Mem Drv RoHS:否 制造商:Texas Instruments 產品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVTH18511DGGR | 功能描述:總線收發(fā)器 Octal 25 Ohm Bus Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74LVTH18512DGGR | 功能描述:特定功能邏輯 Octal 25 Ohm Bus Transceivers RoHS:否 制造商:Texas Instruments 產品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SN74LVTH18512DGGR | 制造商:Texas Instruments 功能描述:SCOPE 18-BIT UNIV BUS TRANSCEIVER |
發(fā)布緊急采購，3分鐘左右您將得到回復。