參數(shù)資料
型號(hào)： SN74ACT3641PQ
廠商： Texas Instruments, Inc.
英文描述： Low-Voltage Quad 2-Input OR Gate with 5V-Tolerant Inputs, Pb-free; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000
中文描述： 1024】36時(shí)鐘先入先出存儲(chǔ)器
文件頁(yè)數(shù)： 1/26頁(yè)
文件大?。?/td> 379K
代理商： SN74ACT3641PQ
SN74ACT3641
1024
×
36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Clocked FIFO Buffering Data From Port A
to Port B
Memory Size: 1024
×
36
Synchronous Read-Retransmit Capability
Mailbox Register in Each Direction
Programmable Almost-Full and
Almost-Empty Flags
Microprocessor Interface Control Logic
Input-Ready and Almost-Full Flags
Synchronized by CLKA
Output-Ready and Almost-Empty Flags
Synchronized by CLKB
Low-Power 0.8-
μ
m Advanced CMOS
Technology
Supports Clock Frequencies up to 67 MHz
Fast Access Times of 11 ns
Pin-to-Pin Compatible With the
SN74ACT3631 and SN74ACT3651
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
description
The SN74ACT3641 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies
up to 67 MHz and has read access times as fast as 12 ns. The 1024
×
36 dual-port SRAM FIFO buffers data
from port A to port B. The FIFO memory has retransmit capability, which allows previously read data to be
accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when
new mail has been stored. Two or more devices are used in parallel to create wider datapaths. Expansion is
also possible in word depth.
The SN74ACT3641 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage synchronized to CLKA. The
output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset
values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.
The SN74ACT3641 is characterized for operation from 0
°
C to 70
°
C.
For more information on this device family, see the following application reports:
FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering
(literature number SCAA009)
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
Metastability Performance of Clocked FIFOs(literature number SCZA004)
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
相關(guān)PDF資料
PDF描述
SN74ACT3651PCB Low-Voltage CMOS Octal Transparent Latch; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Rail; Qty per Container: 75
SN74ACT3651PQ Low-Voltage CMOS Octal Transparent Latch; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500
SN74ACT373DB OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT373FK OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN54ACT373J OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN74ACT3651-15PCB 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ACT3651-15PQ 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ACT3651-20PBC 制造商:Rochester Electronics LLC 功能描述:- Bulk
SN74ACT3651-20PCB 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
SN74ACT3651-20PQ 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*