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參數(shù)資料
| 型號： | SN74ACT3641PQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Low-Voltage Quad 2-Input OR Gate with 5V-Tolerant Inputs, Pb-free; Package: SOEIAJ-14; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2000 |
| 中文描述： | 1024】36時(shí)鐘先入先出存儲器 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 379K |
| 代理商： | SN74ACT3641PQ |
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SN74ACT3641
1024
×
36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS338C – JANUARY 1994 – REVISED OCTOBER 1997
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
almost-full flag (AF)
The AF flag of a FIFO is synchronized to the port clock that writes data to its array (CLKA). The almost-full state
is defined by the contents of register Y. This register is loaded with a preset value during a FIFO reset,
programmed from port A, or programmed serially (see almost-empty flag and almost-full flag offset
programming). The AF flag is low when the number of words in the FIFO is greater than or equal to (1024 – Y).
The AF flag is high when the number of words in the FIFO is less than or equal to [1024 – (Y + 1)]. A data word
present in the FIFO output register has been read from memory.
Two low-to-high transitions of CLKA are required after a FIFO read for its AF flag to reflect the new level of fill.
Therefore, the AF flag of a FIFO containing [1024 – (Y + 1)] or fewer words remains low if two cycles of CLKA
have not elapsed since the read that reduced the number of words in memory to [1024 – (Y + 1)]. An AF flag
is set high by the second low-to-high transition of CLKA after the FIFO read that reduces the number of words
in memory to [1024 – (Y + 1)]. A low-to-high transition of CLKA begins the first synchronization cycle if it occurs
at time t
sk(2)
, or greater, after the read that reduces the number of words in memory to [1024 – (Y + 1)].
Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 9).
synchronous retransmit
The synchronous retransmit feature of the SN74ACT3641 allows FIFO data to be read repeatedly starting at
a user-selected position. The FIFO is first put into retransmit mode to select a beginning word and prevent
ongoing FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three
words can retransmit repeatedly, starting at the selected word. The FIFO can be taken out of retransmit mode
at any time and allow normal device operation.
The FIFO is put in retransmit mode by a low-to-high transition on CLKB when the retransmit mode (RTM) input
is high and OR is high. This rising CLKB edge marks the data present in the FIFO output register as the first
retransmit data. The FIFO remains in retransmit mode until a low-to-high transition occurs while RTM is low.
When two or more reads have been done past the initial retransmit word, a retransmit is initiated by a low-to-high
transition on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the first
retransmit word to the FIFO output register and subsequent reads can begin immediately. Retransmit loops can
be done endlessly while the FIFO is in retransmit mode. RFM must be low during the CLKB rising edge that takes
the FIFO out of retransmit mode.
When the FIFO is put into retransmit mode, it operates with two read pointers. The current read pointer operates
normally, incrementing each time a new word is shifted to the FIFO output register and used by the OR and AE
flags. The shadow read pointer stores the SRAM location at the time the device is put into retransmit mode and
does not change until the device is taken out of retransmit mode. The shadow read pointer is used by the IR
and AF flags. Data writes can proceed while the FIFO is in retransmit mode, but AF is set low by the write that
stores (1024 – Y) words after the first retransmit word. The IR flag is set low by the 1024th write after the first
retransmit word.
When the FIFO is in retransmit mode and RFM is high, a rising CLKB edge loads the current read pointer with
the shadow read-pointer value and the OR flag reflects the new level of fill immediately. If the retransmit changes
the FIFO status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle are
needed to switch AE high (see Figure 11). The rising CLKB edge that takes the FIFO out of retransmit mode
shifts the read pointer used by the IR and AF flags from the shadow to the current read pointer. If the change
of read pointer used by IR and AF should cause one or both flags to transition high, at least two CLKA
synchronizing cycles are needed before the flags reflect the change. A rising CLKA edge after the FIFO is taken
out of retransmit mode is the first synchronizing cycle of IR if it occurs at time t
sk(1)
, or greater, after the rising
CLKB edge (see Figure 12). A rising CLKA edge after the FIFO is taken out of retransmit mode is the first
synchronizing cycle of AF if it occurs at time t
sk(2)
, or greater, after the rising CLKB edge (see Figure 14).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ACT3651-15PCB | 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ACT3651-15PQ | 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ACT3651-20PBC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74ACT3651-20PCB | 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ACT3651-20PQ | 功能描述:先進(jìn)先出 2048 x 36 synch 先進(jìn)先出 Memory RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時(shí)類型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪問時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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