參數(shù)資料
型號: SN74ABT18640DLR
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發(fā)器
英文描述: ABT SERIES, DUAL 9-BIT BOUNDARY SCAN TRANSCEIVER, INVERTED OUTPUT, PDSO56
封裝: GREEN, PLASTIC, SSOP-56
文件頁數(shù): 5/32頁
文件大?。?/td> 638K
代理商: SN74ABT18640DLR
SN54ABT18640, SN74ABT18640
SCAN TEST DEVICES
WITH 18-BIT INVERTING BUS TRANSCEIVERS
SCBS267C – FEBRUARY 1994 – REVISED JULY 1996
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed
while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation
of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 4. Boundary-Control Register Opcodes
BINARY CODE
BIT 2
→ BIT 0
MSB
→ LSB
DESCRIPTION
X00
Sample inputs/toggle outputs (TOPSIP)
X01
Pseudo-random pattern generation/36-bit mode (PRPG)
X10
Parallel-signature analysis/36-bit mode (PSA)
011
Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)
111
Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)
While the control input BSCs (bits 43–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 43–40 of the BSR) control the drive state (active or high impedance) of the selected
device output pins. These BCR instructions are valid only when both bytes of the device are operating in one
direction of data flow (that is, 1OEA
≠ 1OEB and 2OEA ≠ 2OEB) and in the same direction of data flow (that is,
1OEA
= 2OEA and 1OEB = 2OEB). Otherwise, the bypass instruction is performed.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the
associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode
BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated
device I/O pins on each falling edge of TCK.
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