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參數(shù)資料
| 型號： | SN54GTL1655HV |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | GTL/TVC SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 266K |
| 代理商： | SN54GTL1655HV |
SN54GTL1655, SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH LIVE INSERTION
SCBS696E – JULY 1997 – REVISED NOVEMBER 1999
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred
higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels but are not 5-V
tolerant. VREF is the reference input voltage for the B port.
These devices are uniquely partitioned as two 8-bit transceivers with individual latch timing and output signals,
but with a common clock and output enable inputs for both transceiver words.
Data flow for each word is determined by the respective latch enables (xLEAB and xLEBA), output enables
(xOEAB and xOEBA), and clock (CLK). The output enables (1OEAB, 1OEBA, 2OEAB, and 2OEBA) control
byte 1 and byte 2 data for the A-to-B and B-to-A directions, respectively.
For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions
low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK
low-to-high transition. When OEAB is low, the outputs are active. With OEAB high, the outputs are in the
high-impedance state.
Data flow for the B-to-A direction is identical, but uses OEBA, LEBA, and CLK. Note that CLK is common to both
directions and both 8-bit words. OE is also common and is used to disable all I/O ports simultaneously.
The ’GTL1655 is featured with adjustable edge-rate control (VERC). Changing VERC input voltage between GND
and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize for various loading
conditions.
These devices are fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The
Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
The SN54GTL1655 is characterized for operation over the full military temperature range of –55
°C to 125°C.
The SN74GTL1655 is characterized for operation from –40
°C to 85°C.
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