
SN54GTL1655, SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH LIVE INSERTION
SCBS696E – JULY 1997 – REVISED NOVEMBER 1999
13
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V, VREF = 1 V and VERC = VCC or GND for GTL+ (unless otherwise noted)
SN54GTL1655
SN74GTL1655
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
160
MHz
t
Pulse duration
LE high
3
ns
tw
Pulse duration
CLK high or low
3
ns
Data before CLK
↑
2.7
tsu
Setup time
Data before LE
↓
CLK high
2.8
ns
Data before LE
↓
CLK low
2.6
th
Hold time
Data after CLK
↑
0.4
ns
th
Hold time
Data after LE
↓
CLK high or low
0.9
ns
A-to-B switching characteristics over recommended ranges of supply voltage and operating
free-air temperature, VTT = 1.5 V, VREF = 1 V and VERC = VCC or GND for GTL+ (see Figure 1)
PARAMETER
FROM
TO
SN54GTL1655
SN74GTL1655
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
fmax
160
MHz
tPLH
A
B
3
5.1
3
5.1
ns
tPHL
VERC = VCC
B
2.9
6.5
2.9
6.5
ns
tPLH
CLK
B
3.4
5.4
3.4
5.4
ns
tPHL
VERC = VCC
B
2.7
6.2
2.7
6.2
ns
tPLH
LEAB
B
3.5
5.7
3.5
5.7
ns
tPHL
VERC = VCC
B
2.8
6.7
2.8
6.7
ns
ten
OEAB
B
3.3
5.4
3.3
5.4
ns
tdis
OEAB
VERC = VCC
B
3
6.3
3
6.3
ns
ten
OE
B
3
5.5
3
5.5
ns
tdis
OE
VERC = VCC
B
3.6
5.8
3.6
5.8
ns
tPLH
A
B
2.3
4.3
2.3
4.3
ns
tPHL
VERC = GND
B
2
4.4
2
4.4
ns
tPLH
CLK
B
2.7
4.8
2.7
4.8
ns
tPHL
VERC = GND
B
1.9
4.5
1.9
4.5
ns
tPLH
LEAB
B
2.8
4.9
2.8
4.9
ns
tPHL
VERC = GND
B
2.1
4.9
2.1
4.9
ns
ten
OEAB
B
2.5
4.5
2.5
4.5
ns
tdis
OEAB
VERC = GND
B
2.1
4.4
2.1
4.4
ns
ten
OE
B
2.5
4.6
2.5
4.6
ns
tdis
OE
VERC = GND
B
2.9
4.9
2.9
4.9
ns
Slew rate (VERC = VCC)
Both transitions, B outputs (0.6 V to 1.3 V)
1
ns/V
Slew rate (VERC = GND)
Both transitions, B outputs (0.6 V to 1.3 V)
1
ns/V
tsk(o)
Skew between drivers in the same package
(switching in the same direction)
1
ns
tsk(o)
Skew between drivers
switching in any direction in the same package
1
ns
Skew values are applicable for through mode only.
Skew values are applicable for CLK mode only, with all outputs switching simultaneously.
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design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.