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參數(shù)資料
| 型號(hào)： | SN54ALVTH16821WD |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVT SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, CDFP56 |
| 封裝： | 0.380 INCH, CERAMIC, FP-56 |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 196K |
| 代理商： | SN54ALVTH16821WD |
SN54ALVTH16821, SN74ALVTH16821
2.5-V/3.3-V 20-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCES078E – JULY 1996 – REVISED JANUARY 1999
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
SN54ALVTH16821
SN74ALVTH16821
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
150
MHz
tw
Pulse duration, CLK high or low
1.6
1.5
ns
t
Setup time data before CLK
↑
Data high
1.6
1.5
ns
tsu
Setup time, data before CLK
↑
Data low
2.1
2
ns
th
Hold time data after CLK
↑
Data high
0.4
0.3
ns
th
Hold time, data after CLK
↑
Data low
1.1
1
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 2)
SN54ALVTH16821
SN74ALVTH16821
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
150
MHz
tw
Pulse duration, CLK high or low
1.6
1.5
ns
t
Setup time data before CLK
↑
Data high
1.6
1.5
ns
tsu
Setup time, data before CLK
↑
Data low
1.6
1.5
ns
th
Hold time data after CLK
↑
Data high
1.1
1
ns
th
Hold time, data after CLK
↑
Data low
1.1
1
ns
switching characteristics over recommended operating free-air temperature range, CL = 30 pF,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
SN54ALVTH16821
SN74ALVTH16821
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
fmax
150
MHz
tPLH
CLK
Q
1
4.2
1
4.1
ns
tPHL
CLK
Q
1
4.5
1
4.4
ns
tPZH
OE
Q
1.5
4.7
1.5
4.6
ns
tPZL
OE
Q
1
4.2
1
4.1
ns
tPHZ
OE
Q
1.5
4.6
1.5
4.5
ns
tPLZ
OE
Q
1
5
1
4.9
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
TO
SN54ALVTH16821
SN74ALVTH16821
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
MAX
MIN
MAX
UNIT
fmax
150
MHz
tPLH
CLK
Q
1
3.6
1
3.5
ns
tPHL
CLK
Q
1
3.6
1
3.5
ns
tPZH
OE
Q
1
4.2
1
4.1
ns
tPZL
OE
Q
1
3.7
1
3.6
ns
tPHZ
OE
Q
1
4.9
1
4.8
ns
tPLZ
OE
Q
1
4.8
1
4.6
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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