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參數(shù)資料
| 型號(hào)： | SN54ALS323J |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | ALS SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP20 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-20 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大?。?/td> | 693K |
| 代理商： | SN54ALS323J |
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SN54ALS323, SN74ALS323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS
SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54ALS323
SN74ALS323
UNIT
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency (at 50% duty cycle)
0
17
0
17
MHz
tw
Pulse duration
CLK high or low
22
16.5
ns
↑
S0 or S1
25
20
Setup time before CLK
↑
Serial or parallel data
High
18
16
tsu
Setup time before CLK
↑
Serial or parallel data
Low
15
6
ns
su
CLR active
25
20
Inactive-state setup time before CLK
↑
CLR
18
16
th
Hold time after CLK
↑
S0 or S1
0
ns
th
Hold time after CLK
↑
Serial or parallel data
0
ns
Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500
,
R2 = 500
,
TA = MIN to MAX
UNIT
SN54ALS323
SN74ALS323
MIN
MAX
MIN
MAX
fmax
17
MHz
tPLH
CLK
Q
thru Q
2
19
4
13
ns
tPHL
CLK
QA thru QH
4
25
7
19
ns
tPLH
CLK
Q
′ or Q ′
2
21
5
15
ns
tPHL
CLK
QA
′ or QH′
4
25
8
18
ns
tPZH
OE1 OE2
QA thru QH
5
22
6
16
ns
tPZL
OE1, OE2
QA thru QH
6
27
8
22
ns
tPZH
S0 S1
Q
thru Q
5
27
7
17
ns
tPZL
S0, S1
QA thru QH
6
27
8
22
ns
tPHZ
OE1 OE2
Q
thru Q
1
15
1
8
ns
tPLZ
OE1, OE2
QA thru QH
4
38
5
15
ns
tPHZ
S0 S1
QA thru QH
1
16
1
12
ns
tPLZ
S0, S1
QA thru QH
4
34
8
25
ns
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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