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參數(shù)資料
| 型號(hào)： | SN54ALS323J |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | ALS SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP20 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-20 |
| 文件頁(yè)數(shù)： | 10/17頁(yè) |
| 文件大小： | 693K |
| 代理商： | SN54ALS323J |
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SN54ALS323, SN74ALS323
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS
SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FUNCTION TABLE
MODE
INPUTS
I/O PORTS
OUTPUTS
MODE
CLR
S1
S0
OE1
OE2
CLK
SL
SR
A/QA B/QB C/QC D/QD E/QE
F/QF G/QG H/QH
QA
′
QH
′
Clear
L
X
L
H
L
X
H
L
X
L
X
↑
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
Hold
H
L
X
L
X
L
X
L
X
QA0
QB0
QC0
QD0
QE0
QF0
QG0
QH0
QA0
QH0
Shift
Right
H
L
H
L
↑
X
H
L
H
L
QAn
QBn
QCn
QDn
QEn
QFn
QGn
H
L
QGn
Shift
Left
H
L
↑
H
L
X
QBn
QCn
QDn
QEn
QFn
QGn
QHn
H
L
QBn
H
L
Load
H
X
↑
X
a
b
c
d
e
f
g
h
a
h
NOTE: a ...h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs
are isolated from the I/O terminals.
When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
logic symbol
SRG8
M
0
3
4R
9
6
14
5
15
4
8
2
3
0
1
S0
1
19
S1
12
CLK
5, 13
1,4D
11
SR
3,4D
7
6, 13
3, 4D
13
17
12, 13
2, 4D
18
SL
3, 4D
16
&
3EN13
C4/1
→/2←
QA
′
QH
′
CLR
OE1
OE2
A/QA
H/QH
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG
Z5
Z6
Z12
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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