參數(shù)資料
型號: SN0305042RTHR
廠商: TEXAS INSTRUMENTS INC
元件分類: 時鐘及定時
英文描述: 1803 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC24
封裝: GREEN, PLASTIC, VQFN-24
文件頁數(shù): 8/26頁
文件大小: 606K
代理商: SN0305042RTHR
www.ti.com
IN
CLK
CAC
IN
CDCM1804
CCT
VBB
Rdc
NOTE: CAC AC-coupling capacitor (e.g., 10 nF)
CCT Capacitor keeps voltage at IN constant (e.g., 10 nF)
Rdc Load and correct duty cycle (e.g., 50 )
VBB Bias voltage output
S0087-01
DEVICE BEHAVIOR DURING RESET AND CONTROL-TERMINAL SWITCHING
Output Behavior From Enabling the Device (EN = 0
→ 1)
CDCM1804
SCAS697E – JULY 2003 – REVISED MAY 2005
APPLICATION INFORMATION (continued)
Figure 14. Typical Application Setting for Single-Ended Input Signals Driving the CDCM1804
In disable mode (EN = 0), all output drivers are switched in high-Z mode. The S[2:0] control inputs are also
switched off. In the same mode, all flip-flops are reset. The typical current consumption is below 500
A.
When the device is enabled again, it takes typically 1
s for the settling of the reference voltage and currents.
During this time, the outputs Y[2:0] and Y[2:0] drive a high signal. Y3 is unknown (could be high or low). After the
settle time, the outputs go into the low state. Due to the synchronization of each output driver signal with the
input clock, the state of the waveforms after enabling the device is as shown in Figure 15. The inverting input
and output signal are not included. The Y:/1 waveform is the undivided output driver state.
16
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