參數(shù)資料
型號: SN0305042RTHR
廠商: TEXAS INSTRUMENTS INC
元件分類: 時鐘及定時
英文描述: 1803 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC24
封裝: GREEN, PLASTIC, VQFN-24
文件頁數(shù): 7/26頁
文件大?。?/td> 606K
代理商: SN0305042RTHR
www.ti.com
APPLICATION INFORMATION
LVPECL RECEIVER INPUT TERMINATION
IN
150
150
CAC
50
50
IN
CDCM1804
C
VBB
50
50
S0085-01
LVPECL
130
83
CDCM1804
50
50
130
83
S0086-01
IN
CDCM1804
SCAS697E – JULY 2003 – REVISED MAY 2005
The input of the CDCM1804 has a high impedance and comes with a large common-mode voltage range.
For optimized noise performance, it is recommended to properly terminate the PCB trace (transmission line). If a
differential signal drives the CDCM1804, then a 100-
termination resistor is recommended to be placed as
close as possible across the input terminals. An even better approach is to install 2 × 50
, with the center tap
connected to a capacitor (C) to terminate odd-mode noise and make up for transmission-line mismatches. The
VBB output can also be connected to the center tap to bias the input signal to (VDD – 1.3 V) (see Figure 12).
Figure 12. Recommended AC-Coupling LVPECL Receiver Input Termination
Figure 13. Recommended DC-Coupling LVPECL Receiver Input Termination
The CDCM1804 can also be driven by single-ended signals. Typically, the input signal becomes connected to
one input, while the complementary input must be properly biased to the center voltage of the incoming input
signal. For LVCMOS signals, this would be VCC/2, realized by a simple voltage divider (e.g., two 10-k resistors).
The best option (especially if the dc offset of the input signal might vary) is to ac-couple the input signal and then
rebias the signal using the VBB reference output. See Figure 14.
15
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