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參數(shù)資料
| 型號(hào)： | SN0305042RTHR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 1803 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC24 |
| 封裝： | GREEN, PLASTIC, VQFN-24 |
| 文件頁數(shù)： | 20/26頁 |
| 文件大?。?/td> | 606K |
| 代理商： | SN0305042RTHR |
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CONTROL TERMINAL SETTINGS
CDCM1804
SCAS697E – JULY 2003 – REVISED MAY 2005
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
EN
1
I
ENABLE: Enables or disables all outputs simultaneously. The EN terminal offers three
(with 60-k
pullup)
different configurations: tied to GND (logic 0), external 60-k
pulldown resistor (pull to
VDD/2), or left floating (logic 1);
EN = 1: outputs on according to S[2:0] settings
EN = VDD/2: outputs on according to S[2:0] settings
EN = 0: outputs Y[3:0] off (high impedance)
See Table 1 for details.
IN, IN
3, 4
I (differential)
Differential input clock: Input stage is sensitive and has a wide common-mode range.
Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS,
CML, HSTL). Because the input is high-impedance, it is recommended to terminate the
PCB transmission line before the input (e.g., with 100
across input). Input can also be
driven by single-ended signal if the complementary input is tied to VBB. A
more-advanced scheme for single-ended signals is given in the Application Information
section near the end of this document.
The inputs employ an ESD structure protecting the inputs in case of an input voltage
exceeding the rails by more than ~0.7 V. Reverse biasing of the IC through these inputs
is possible and must be prevented by limiting the input voltage < VDD.
S[2:0]
18, 19, 24
I
Select mode of operation: Defines the output configuration of Y[3:0]. Each terminal
(with 60-k
pullup)
offers three different configurations: tied to GND (logic 0), external 60-k
pulldown
VBB
6
O
Bias voltage output to be used to bias unused complementary input IN for single-ended
input signals.
The output voltage of VBB is VDD – 1.3 V. When driving a load, the output current drive
is limited to about 1.5 mA.
VSS
7
Supply
Device ground
VDDPECL
2, 5
Supply
Supply voltage LVPECL input + internal logic
VDD[2:0]
8, 11, 14,
Supply
LVPECL output supply voltage for output Y[2:0]. Each output can be disabled by pulling
17, 20, 23
the corresponding VDDx to GND.
CAUTION: In this mode, no voltage from outside may be forced, because internal
diodes could be forced in forward direction. Thus, it is recommended to disconnect the
output.
VDD3
13
Supply
Supply voltage LVCMOS output. The LVCMOS output can be disabled by pulling VDD3
to GND.
CAUTION: In this mode, no voltage from outside may be forced because internal
diodes could be forced in a forward direction. Thus, it is recommended to leave Y3
unconnected, tied to GND, or terminated into GND.
Y[2:0]
9, 15, 21
O (LVPECL)
LVPECL clock outputs. These outputs provide low-skew copies of IN or down-divided
Y[2:0]
10, 16, 22
copies of clock IN based on selected mode of operation S[2:0]. If an output is unused,
the output can simply be left open to save power and minimize noise impact to the
remaining outputs.
Y3
12
O
LVCMOS clock output. This output provides copy of IN or down-divided copy of clock IN
based on selected mode of operation S[2:0]. Also, this output can be disabled when
VDD3 becomes tied to GND.
The CDCM1804 has three control terminals (S0, S1, and S2) and an enable terminal (EN) to select different
output mode settings. All four inputs (S0, S1, S2, and EN) are 3-level inputs offering 54 different combinations. In
addition, the EN input allows the disabling of all outputs and forcing them into a high-z (or 3-state) output state
when pulled to GND.
Each control input incorporates a 60-k
pullup resistor. Thus, it is easy to choose the input setting by designing
a resistor pad between the control input and GND. To choose a logic zero, the resistor value must be zero.
Setting the input high requires leaving the resistor pad empty (no resistor installed). For setting the input to
VDD/2, the installed resistor must be a 60-k pulldown to GND with a 10% tolerance or better.
3
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|---|---|
| SN0305042RTHT | 功能描述:時(shí)鐘緩沖器 1:3 LVPECL Clock Bfr & Add LVCMOS Out RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SN0306011PPM | 制造商:Texas Instruments 功能描述: |
| SN0307009BGHK | 制造商:Texas Instruments 功能描述: |
| SN0307009BZHK | 制造商:Texas Instruments 功能描述: |
| SN0307009GHK | 制造商:Texas Instruments 功能描述: |
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