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參數(shù)資料
| 型號(hào)： | SMS44S |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Highly Programmble Voltage Supervisory Circuit |
| 中文描述： | 高度可編程電壓監(jiān)控電路 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 401K |
| 代理商： | SMS44S |
8
SMS44
2047 2.3 10/23/00
SUMMIT MICROELECTRONICS, Inc.
Table 7. PUP Delays
Longdog timer will generally be programmed to be of
longer duration than the watchdog and it will generate a
reset if it times out. Both timers are cleared by a low to high
transition on WLDI and they both start simultaneously.
If the watchdog should timeout the device status will be
recorded in the status register. If the Longdog times out
RESET# will drive low either until a WLDI clear is received
or until t
PRTO
(whichever occurs first), at which time it will
return high. Refer to Figures 3 and 4 illustrating the action
of RESET# and IRQ# with respect to the Watchdog and
Longdog timers and the WLDI input.
If WLDI is held low the timers will free-run generating a
series of interrupts and resets. If WLDI is held high the
interrupt (watchdog) output will be disabled and only the
reset (Longdog) output will be active.
2047 Table04 1.0
7
S
E
x
x
x
x
x
x
x
x
0
1
B
Q
M
S
6
5
4
3
2
1
0
S
D
B
0
L
W
f
O
s
m
0
0
6
1
m
0
0
2
3
m
0
0
4
6
2
=
5
=
0
1
=
0
2
=
c
n
e
u
q
e
S
n
e
u
q
e
S
1
O
x
x
x
x
0
0
1
1
x
x
T
R
0
O
x
x
x
x
0
1
0
1
x
x
T
R
1
D
0
0
1
1
x
x
x
x
x
x
L
0
D
0
1
0
1
x
x
x
x
x
x
L
2
L
D
W
1
D
g
o
d
g
n
o
W
s
s
m
5
m
0
0
0
e
e
c
t
t
O
T
R
P
s
s
O
T
R
P
t
t
O
T
R
P
s
s
n
f
m
m
O
O
O
T
R
P
Table 4. Configuration Register 6
When the Longdog times out, a reset will be generated.
When reset returns high (after t
PRTO
or after a WLDI
strobe) both timers are reset to time zero. Therefore, if the
Longdog t
PLDTO
is equal to or shorter than the watchdog
t
PWDTO
, the reset will effectively clear the interrupt before
it can drive the output low.
Register 6 is also used to set the programmable reset
timeout period (t
PRTO
) and to select the sequence option.
Sequence Delay Programming
The sequence delays are programmed in register 7. Bit 7
of register 6, must be set to a
“
0
”
in order to enable the
sequencing of the PUP# outputs. Sequencing will not
commence until V
0
is above its programmed threshold.
Each PUP# (-3, -2 and -1) is delayed according to the
states of its Bit 1 and Bit 0 as indicated in Table 7.
Refer to Figures 5 and 6 for the detailed timing relationship
of the programmable power-on sequencing.
2047 Table06 1.0
2047 Table07 1.0
7
S
E
B
Q
M
S
6
5
4
3
2
1
0
S
D
0
1
0
1
0
1
B
0
L
W
1
O
T
R
0
O
T
R
1
O
0
0
8
6
1
2
3
4
6
D
L
0
D
L
2
D
0
0
1
1
1
1
W
1
D
0
1
0
0
1
1
2047 Table05 1.0
W
F
m
m
0
0
0
0
0
0
0
F
0
s
s
4
s
s
s
m
m
m
Table 5. Configuration Register 6
Table 6. Configuration Register 7
1
t
B
0
t
B
t
Y
L
D
)
P
X
0
0
y
a
D
n
s
m
0
0
1
y
a
D
s
m
5
2
1
0
y
a
D
s
m
0
5
1
1
y
a
D
s
m
0
0
1
7
S
B
M
6
5
4
3
2
1
0
S
B
L
s
s
e
t
r
d
d
e
S
A
e
S
2
#
P
U
P
1
s
s
e
d
a
&
2
A
d
e
s
a
e
d
a
e
p
y
2
A
d
e
s
a
a
e
n
o
g
o
C
n
o
g
o
C
#
P
U
P
3
0
#
P
U
P
1
c
e
D
y
o
c
e
D
y
o
1
0
s
s
n
s
d
n
o
p
s
e
o
n
m
o
c
e
a
n
e
e
w
/
c
o
e
w
/
a
e
#
P
U
P
1
p
s
o
n
m
o
c
,
1
0
1
1
A
k
c
o
L
0
S
A
0
0
1
x
0
d
n
o
e
,
1
1
e
p
y
e
A
o
x
1
s
s
&
e
s
n
o
0
1
x
x
d
t
o
d
e
k
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