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參數(shù)資料
| 型號(hào)： | SMS44S |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Highly Programmble Voltage Supervisory Circuit |
| 中文描述： | 高度可編程電壓監(jiān)控電路 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 401K |
| 代理商： | SMS44S |
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7
2047 2.3 10/23/00
SMS44
SUMMIT MICROELECTRONICS, Inc.
Table 1. Configuration Register 4
DEVICE OPERATION
2047 Table01 1.0
SUPPLY AND MONITOR FUNCTIONS
The V
0
, V
1
, V
2
and V
3
inputs are internally diode-ORed so
that any one of the four can act as the device supply. The
RESET# output will be guaranteed true so long as one of
the four pins is at or above 1V.
Note
: or performing a memory operation (read or
write) and to have the ability to change configura-
tion register contents at least one supply input
must be above 2.7V.
If sequencing is enabled, the designer must insure V
0
is
the primary supply and is the first to become active.
Associated with each input is a comparator with a pro-
grammable threshold for detection of under-voltage con-
ditions on any of the four supply inputs. The threshold can
be programmed in 20mV increments anywhere within the
range of 0.9V to 6.0V. Configuration registers 0, 1, 2, and
3 adjust the thresholds for V
0
, V
1
, V
2
and V
3
respectively.
If the value contained in the register is all zeroes, the
corresponding threshold will be 0.9V. If the contents were
05
HEX
the threshold would then be 1.0V [0.9V + (5
×
0.02V)]. All four registers are configured as 8-bit registers.
RESET AND IRQ FUNCTIONS
Both the reset and interrupt outputs have four program-
mable sources for activation. Configuration register 4 is
used for selecting the activation source, which can be any
combination of V
0
, V
1
, V
2
and V
3
. A monitor input can only
be programmed to activate on either an under-voltage or
over-voltage condition, but not both conditions.
The RESET# output has two hardwired sources for activa-
tion: the MR# input, and the expiration of the Longdog
timer. RESET# will remain active so long as MR# is low,
and will continue driving the RESET# output for t
PRTO
(programmable reset time out) after MR# returns high.
The MR# input cannot be bypassed or disabled. The
Longdog timer can be bypassed by programming it to the
off or idle mode.
The watchdog is the sole hardwired source for driving the
IRQ# output low. It can effectively be bypassed by
programming it to the off or idle mode. Refer to Figures 1,
2, 3 and 4 for a detailed illustration of the relationships
among the affected signals.
The SMS44 also provides the option of the monitors
triggering on either an under-voltage or over-voltage con-
dition. The low-order four bits of configuration register 5
program these options.
The high order four bits of configuration register 5 are read
only, and their state indicates the sources of interrupts.
Whenever an interrupt is generated the status of the V
inputs will be recorded in the status register. The status
will remain in the register until the device is powered-down
7
S
V
3
R
B
M
6
5
4
3
2
1
0
S
V
0
e
B
L
V
2
g
T
E
S
E
V
1
V
0
e
V
3
V
2
g
V
1
S
c
o
S
r
g
c
o
r
g
Q
R
I
or another interrupt occurs that overwrites the previous
status.
If an interrupt occurs and no bits are set the default
assumption must be the watchdog generated the inter-
rupt.
WATCHDOG AND LONGDOG TIMERS
The SMS44 contains two timers that can be programmed
independently. The Watchdog is intended to be of shorter
duration and will generate an interrupt if it times out. The
3
S
V
3
B
M
2
1
0
S
V
0
B
L
V
2
V
1
s
n
e
a
n
e
o
e
d
n
V
d
e
e
s
1
a
g
n
W
e
g
a
v
v
o
e
e
s
e
h
0
a
g
g
n
W
v
d
n
u
h
r
e
a
t
p
e
0
0
0
0
s
e
a
n
e
o
e
d
V
d
r
n
t
p
n
1
1
1
1
2047 Table03 1.0
2047 Table02 1.0
Table 2. Configuration Register 5
7
S
V
3
0
B
M
6
5
4
S
V
0
0
B
L
V
2
0
V
1
0
e
h
t
s
e
c
u
e
n
1
a
h
g
e
n
a
e
R
o
s
c
1
1
1
1
Table 3. Configuration Register 5
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