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參數(shù)資料
| 型號： | SMS44S |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Highly Programmble Voltage Supervisory Circuit |
| 中文描述： | 高度可編程電壓監(jiān)控電路 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 401K |
| 代理商： | SMS44S |
10
SMS44
2047 2.3 10/23/00
SUMMIT MICROELECTRONICS, Inc.
The delay from V
PTH0
until PUP#1 low is t
PDLY1
. There is
a similar t
PDLY
X delay for V1 to PUP#2 and V2 to PUP#3.
They are programmed in register 7. See Figure 5.
Sequencing will always occur as indicated in the flow
chart.
MEMORY OPERATION
Data for the configuration registers and the memory array
are read and written via an industry standard two-wire
interface. The bus was designed for two-way, two-line
serial communication between different integrated cir-
cuits. The two lines are a serial data line (SDA) and a serial
clock line (SCL). The SDA line must be connected to a
positive supply by a pull-up resistor, located somewhere
on the bus. See Memory Operating Characteristics:
Table 8 and Figure 8.
Figure 7. Sequence Flow Chart
Yes
No
Sequencing
Enabled
V
0
>V
PTH
Turn On PUP#1
2047 Fig07 2.1
t
PDLY1
Yes
No
V1
>V
PTH
Turn On PUP#2
t
PDLY2
Yes
No
V2
>V
PTH
Turn On PUP#3
t
PDLY3
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相關(guān)代理商/技術(shù)參數(shù) |
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| SMS45 | 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Quad Programmable Precision Cascade Sequencer and Supervisory Controller with 4k-Bit Nonvolatile Memory |
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| SMS-450-RED-50MM | 制造商:3M Electronic Products Division 功能描述:80610754741 |
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