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參數(shù)資料
| 型號(hào)： | SMQ320C32PCM60 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 32-BIT, 60 MHz, OTHER DSP, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁(yè)數(shù)： | 29/43頁(yè) |
| 文件大?。?/td> | 594K |
| 代理商： | SMQ320C32PCM60 |
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027C – APRIL 1998 – REVISED OCTOBER 2001
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
serial-port timing
serial-port timing [P = tc(H)] (see Figure 29 and Figure 30)
NO
’320C32-50
’320C32-60
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
65
td(H1-SCK)
Delay time, H1 high to internal
CLKX/R high/low
10
8
ns
66
t
Cycle time,
CLKX/R ext
2.6P
ns
66
tc(SCK)
Cycle time,
CLKX/R
CLKX/R int
2P
(232)P
2P
(232)P
ns
67
t
Pulse duration,
CLKX/R ext
P + 10
ns
67
tw(SCK)
Pulse duration,
CLKX/R high/low
CLKX/R int
[tc(SCK)/2]–5
[tc(SCK)/2]+5
[tc(SCK)/2]–5
[tc(SCK)/2]+5
ns
68
tr(SCK)
Rise time, CLKX/R
6
5
ns
69
tf(SCK)
Fall time, CLKX/R
6
5
ns
70
t
Delay time, CLKX
CLKX ext
24
20
ns
70
td(DX)
Delay time, CLKX
to DX valid
CLKX int
16
15
ns
71
t
Setup time, DR
CLKR ext
9
8
ns
71
tsu(DR)
Setu time, DR
before CLKR low
CLKR int
17
15
ns
72
t
Hold time, DR
CLKR ext
7
6
ns
72
th(DR)
Hold time, DR
from CLKR low
CLKR int
0
ns
73
t
Delay time, CLKX
to internal FSX
CLKX ext
22
20
ns
73
td(FSX)
to internal FSX
high/low
CLKX int
15
14
ns
74
t
Setup time, FSR
CLKR ext
7
6
ns
74
tsu(FSR)
Setu time, FSR
before CLKR low
CLKR int
7
6
ns
75
t
Hold time, FSX/R
input from
CLKX/R ext
7
6
ns
75
th(FS)
input from
CLKX/R low
CLKX/R int
0
ns
76
t
Setup time,
external FSX
CLKX ext
8–P
[tc(SCK)/2]–10*
8–P
[tc(SCK)/2]–10*
ns
76
tsu(FSX)
external FSX
before CLKX high
CLKX int
21–P
tc(SCK)/2*
21–P
tc(SCK)/2*
ns
77
t
Delay time, CLKX
to first DX bit, FSX
CLKX ext
24*
20*
ns
77
td(CH-DX)V
to first DX bit, FSX
precedes CLKX
high
CLKX int
14*
12*
ns
78
td(FSX-DX)V
Delay time, FSX to first DX bit,
CLKX precedes FSX
24*
20*
ns
79
td(DXZ)
Delay time, CLKX high to DX in
the high-impedance state
following last data bit
14*
12*
ns
* This parameter is not production tested.
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