參數(shù)資料
型號： SMQ320C32PCM60
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 32-BIT, 60 MHz, OTHER DSP, PQFP144
封裝： PLASTIC, QFP-144
文件頁數(shù)： 28/43頁
文件大?。?/td> 594K
代理商： SMQ320C32PCM60
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027C – APRIL 1998 – REVISED OCTOBER 2001
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing for IACK (see Notes 6, 7, and Figure 28)
NO
’320C32-50
’320C32-60
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
63
td(H1H-IACKL)
Delay time, H1 high to IACK low
7
6
ns
64
td(H1H-IACKH)
Delay time, H1 high to IACK high
7
6
ns
NOTES:
6. IACK is active for the entire duration of the bus cycle and is extended if the bus cycle utilizes wait states.
7. IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle
(H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if the decode
phase of the IACK instruction is extended.
H3
H1
IACK
A
D
63
64
Fetch IACK
Instruction
IACK Data
Read
Decode IACK
Instruction
Figure 28. IACK Timing
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