參數(shù)資料
型號(hào)： SMJ320C6414DGADW60
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, CPGA570
封裝： 33 X 33 MM, CERAMIC, FCPGA-570
文件頁(yè)數(shù)： 70/134頁(yè)
文件大?。?/td> 1997K
代理商： SMJ320C6414DGADW60
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SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
40
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
DEVICE CONFIGURATIONS (CONTINUED)
Table 29. C6414, C6415, and C6416 Device Multiplexed Pins
MULTIPLEXED PINS
DEFAULT FUNCTION
DEFAULT SETTING
DESCRIPTION
NAME
NO.
DEFAULT FUNCTION
DEFAULT SETTING
DESCRIPTION
CLKOUT4/GP1
Y7
CLKOUT4
GP1EN = 0 (disabled)
These pins are software-configurable.
To use these pins as GPIO pins, the
GPxEN bits in the GPIO Enable
CLKOUT6/GP2
T10
CLKOUT6
GP2EN = 0 (disabled)
GPxEN bits in the GPIO Enable
Register and the GPxDIR bits in the
GPIO
Direction
Register
must
be
properly configured.
CLKS2/GP8
W7
CLKS2
GP8EN = 0 (disabled)
properly configured.
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
GP9/PIDSEL
K6
To use GP[15:9] as GPIO pins, the PCI
needs to be disabled (PCI_EN = 0), the
GP10/PCBE3
L7
To use GP[15:9] as GPIO pins, the PCI
needs to be disabled (PCI_EN = 0), the
GPxEN bits in the GPIO Enable
GP11/PREQ
H6
GPxEN = 0 (disabled)
GPxEN bits in the GPIO Enable
Register and the GPxDIR bits in the
GP12/PGNT
J7
None
GPxEN = 0 (disabled)
PCI_EN = 0 (disabled)
Register and the GPxDIR bits in the
GPIO
Direction
Register
must
be
properly configured.
GP13/PINTA
G4
None
PCI_EN = 0 (disabled)
GPIO
Direction
Register
must
be
properly configured.
GPxEN = 1: GPx pin enabled
GP14/PCLK
G5
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GP15/PRST
J8
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
DX1/UXADDR4
Y10
DX1
FSX1/UXADDR3
AA11
FSX1
By default, McBSP1 is enabled upon
FSR1/UXADDR2
AA8
FSR1
UTOPIA_EN (BEA11) = 0
By default, McBSP1 is enabled upon
reset (UTOPIA is disabled).
To enable the UTOPIA peripheral, an
DR1/UXADDR1
V11
DR1
UTOPIA_EN (BEA11) = 0
(disabled)
reset (UTOPIA is disabled).
To enable the UTOPIA peripheral, an
external pullup resistor (1 k
) must be
CLKX1/URADDR4
T12
CLKX1
(disabled)
external pullup resistor (1 k
) must be
provided on the BEA11 pin (setting
CLKS1/URADDR3
Y8
CLKS1
provided on the BEA11 pin (setting
UTOPIA_EN = 1 at reset).
CLKR1/URADDR2
AB7
CLKR1
UTOPIA_EN = 1 at reset).
CLKX2/XSP_CLK
W5
CLKX2
DR2/XSP_DI
Y4
DR2
DX2/XSP_DO
R9
DX2
HD[31:0]/AD[31:0]
§
HD[31:0]
HAS/PPAR
N7
HAS
By default, HPI is enabled upon reset
HCNTL1/PDEVSEL
N8
HCNTL1
By default, HPI is enabled upon reset
(PCI is disabled).
HCNTL0/PSTOP
P5
HCNTL0
PCI_EN = 0 (disabled)
(PCI is disabled).
To enable the PCI peripheral an external
HDS1/PSERR
R5
HDS1
PCI_EN = 0 (disabled)
To enable the PCI peripheral an external
pullup resistor (1 k
) must be provided
on the PCI_EN pin (setting PCI_EN = 1
HDS2/PCBE1
P6
HDS2
pullup resistor (1 k ) must be provided
on the PCI_EN pin (setting PCI_EN = 1
at reset).
HR/W/PCBE2
N6
HR/W
at reset).
HWWIL/PTRDY
N5
HHWIL (HPI16 only)
HINT/PFRAME
P4
HINT
HCS/PPERR
N9
HCS
HRDY/PIRDY
N4
HRDY
For the C6415 and C6416 devices, all other standalone UTOPIA and PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled
[UTOPIA_EN (BEA11) = 0 or PCI_EN = 0].
The C6414 device does not support the PCI and UTOPIA peripherals. These are the only multiplexed pins on the C6414 device, all other pins
are standalone peripheral functions and are not MUXed.
§ For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
相關(guān)PDF資料
PDF描述
SM320C6414DGADW60 64-BIT, 75 MHz, OTHER DSP, CPGA570
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