參數(shù)資料
型號(hào): SMJ320C6414DGADW60
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, CPGA570
封裝: 33 X 33 MM, CERAMIC, FCPGA-570
文件頁數(shù): 104/134頁
文件大?。?/td> 1997K
代理商: SMJ320C6414DGADW60
SMJ320C6414, SMJ320C6415, SMJ320C6416
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SGUS050A JANUARY 2004 REVISED MARCH 2004
71
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
power-down mode logic
Figure 8 shows the power-down mode logic on the C6414/C6415/C6416.
PWRD
Internal Clock Tree
CPU
IFR
IER
CSR
PD1
PD2
Power-
Down
Logic
Clock
PLL
CLKIN
RESET
CLKOUT6
PD3
Internal
Peripherals
CLKOUT4
Clock
and Dividers
Distribution
External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
SMJ320C6414/15/16
Figure 8. Power-Down Mode Logic
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 1510)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 9 and described in Table 33.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU
and Instruction Set Reference Guide (literature number SPRU189).
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