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參數(shù)資料
| 型號： | SMJ320C6201BGLPW20 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 200 MHz, OTHER DSP, CBGA429 |
| 封裝： | CERAMIC, MO-156, BGA-429 |
| 文件頁數(shù)： | 47/66頁 |
| 文件大?。?/td> | 971K |
| 代理商： | SMJ320C6201BGLPW20 |
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B – APRIL 2000 – REVISED AUGUST 2001
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP(see Figure 32)
NO
C6201B
UNIT
NO.
MIN
MAX
UNIT
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
*2P
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
*P – 1
ns
5
t
Set p time e ternal FSR high before CLKR lo
CLKR int
*9
ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR ext
2
ns
6
t
Hold time e ternal FSR high after CLKR lo
CLKR int
*6
ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR ext
3
ns
7
t
Set p time DR alid before CLKR lo
CLKR int
8
ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR ext
1
ns
8
t
Hold time DR alid after CLKR lo
CLKR int
3
ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR ext
4
ns
10
t
Setup time external FSX high before CLKX low
CLKX int
9
ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX ext
2
ns
11
t
Hold time e ternal FSX high after CLKX lo
CLKX int
6
ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX ext
3
ns
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
*Not production tested
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| SM320C6201BGLPW20 | 32-BIT, 200 MHz, OTHER DSP, CBGA429 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ320C6201BS14 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
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| SMJ320C6203 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PORCESSOR |
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