參數(shù)資料
型號(hào)： SMJ320C6201BGLPW20
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 200 MHz, OTHER DSP, CBGA429
封裝： CERAMIC, MO-156, BGA-429
文件頁(yè)數(shù)： 32/66頁(yè)
文件大?。?/td> 971K
代理商： SMJ320C6201BGLPW20
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B – APRIL 2000 – REVISED AUGUST 2001
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 17)
NO
C6201B
UNIT
NO.
MIN
MAX
UNIT
7
tsu(EDV-SSCLKH)
Setup time, read EDx valid before SSCLK high
2.5
ns
8
th(SSCLKH-EDV)
Hold time, read EDx valid after SSCLK high
1.5
ns
switching characteristics for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 17 and Figure 18)
NO
PARAMETER
C6201B
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
tosu(CEV-SSCLKH)
Output setup time, CEx valid before SSCLK high
1.5P – 3
ns
2
toh(SSCLKH-CEV)
Output hold time, CEx valid after SSCLK high
0.5P – 1.5
ns
3
tosu(BEV-SSCLKH)
Output setup time, BEx valid before SSCLK high
1.5P – 3
ns
4
toh(SSCLKH-BEIV)
Output hold time, BEx invalid after SSCLK high
*0.5P – 1.5
ns
5
tosu(EAV-SSCLKH)
Output setup time, EAx valid before SSCLK high
1.5P – 3
ns
6
toh(SSCLKH-EAIV)
Output hold time, EAx invalid after SSCLK high
*0.5P – 1.5
ns
9
tosu(ADSV-SSCLKH)
Output setup time, SSADS valid before SSCLK high
1.5P – 3
ns
10
toh(SSCLKH-ADSV)
Output hold time, SSADS valid after SSCLK high
0.5P – 1.5
ns
11
tosu(OEV-SSCLKH)
Output setup time, SSOE valid before SSCLK high
1.5P – 3
ns
12
toh(SSCLKH-OEV)
Output hold time, SSOE valid after SSCLK high
0.5P – 1.5
ns
13
tosu(EDV-SSCLKH)
Output setup time, EDx valid before SSCLK high
1.5P – 3
ns
14
toh(SSCLKH-EDIV)
Output hold time, EDx invalid after SSCLK high
*0.5P – 1.5
ns
15
tosu(WEV-SSCLKH)
Output setup time, SSWE valid before SSCLK high
1.5P – 3
ns
16
toh(SSCLKH-WEV)
Output hold time, SSWE valid after SSCLK high
0.5P – 1.5
ns
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
*Not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
相關(guān)PDF資料
PDF描述
SM320C6201BGLPW20 32-BIT, 200 MHz, OTHER DSP, CBGA429
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