參數(shù)資料
型號(hào)： SMJ320C6201BGLPW20
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 32-BIT, 200 MHz, OTHER DSP, CBGA429
封裝： CERAMIC, MO-156, BGA-429
文件頁(yè)數(shù)： 43/66頁(yè)
文件大?。?/td> 971K
代理商： SMJ320C6201BGLPW20
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B – APRIL 2000 – REVISED AUGUST 2001
48
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles (see Figure 28, Figure 29, Figure 30, and
Figure 31)
NO
C6201B
UNIT
NO.
MIN
MAX
UNIT
1
tsu(SEL-HSTBL)
Setup time, select signals§ valid before HSTROBE low
4
ns
2
th(HSTBL-SEL)
Hold time, select signals§ valid after HSTROBE low
2
ns
3
tw(HSTBL)
Pulse duration, HSTROBE low
2P
ns
4
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
*2P
ns
10
tsu(SEL-HASL)
Setup time, select signals§ valid before HAS low
4
ns
11
th(HASL-SEL)
Hold time, select signals§ valid after HAS low
2
ns
12
tsu(HDV-HSTBH)
Setup time, host data valid before HSTROBE high
4
ns
13
th(HSTBH-HDV)
Hold time, host data valid after HSTROBE high
2
ns
14
th(HRDYL-HSTBL)
Hold time, HSTROBE low after HRDY low. HSTROBE shoul not be inactivated
until HRDY is active (low); otherwise, HPI writes will not complete properly.
*1
ns
18
tsu(HASL-HSTBL)
Setup time, HAS low before HSTROBE low
*2
ns
19
th(HSTBL-HASL)
Hold time, HAS low after HSTROBE low
*2
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
*Not production tested.
switching characteristics during host-port interface cycles (see Figure 28, Figure 29, Figure 30,
and Figure 31)
NO
PARAMETER
C6201B
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
5
td(HCS-HRDY)
Delay time, HCS to HRDY
*1
9
ns
6
td(HSTBL-HRDYH)
Delay time, HSTROBE low to HRDY high#
*3
12
ns
7
toh(HSTBL-HDLZ)
Output hold time, HD low impedance after HSTROBE low for an HPI read
*4
ns
8
td(HDV-HRDYL)
Delay time, HD valid to HRDY low
*P – 3
*P + 3
ns
9
toh(HSTBH-HDV)
Output hold time, HD valid after HSTROBE high
*1
*12
ns
15
td(HSTBH-HDHZ)
Delay time, HSTROBE high to HD high impedance
*3
*12
ns
16
td(HSTBL-HDV)
Delay time, HSTROBE low to HD valid
*2
*12
ns
17
td(HSTBH-HRDYH)
Delay time, HSTROBE high to HRDY high||
*3
12
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 200 MHz, use P = 5 ns.
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
# This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.
|| This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
*Not production tested.
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