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參數(shù)資料
| 型號： | SMD1108F |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device |
| 中文描述： | 8通道自動監(jiān)控ADC的在系統(tǒng)可編程模擬（ISPA）設(shè)備 |
| 文件頁數(shù)： | 7/29頁 |
| 文件大小： | 734K |
| 代理商： | SMD1108F |
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7
2052 2.0 10/05/01
SMD1108
Preliminary
SUMMIT MICROELECTRONICS, Inc.
THE ADC AND THE ANALOG SWITCH
10-bit ADC
The 10-bit ADC is a self-clocking SAR implementation. In
the manual mode of conversion the sample and hold
operation will begin after the SMD1108 has received the
request for conversion and the channel address. See
Table 1.
8 Analog Channels
The eight analog channels can be separated into two
function blocks: the bottom four channels (V
CC0
/CH4 to
V
CC3
/CH7) are primarily supply voltage monitors; the top
four channels (CH0 to CH3) are primarily environmental
monitors. All eight channels can be switched to the 10-bit
ADC and have their inputs converted on-command. CH0
to CH3 may be placed in the Auto-Monitor mode.
V
CC0
/CH4 to V
CC3
/CH7 provide four inputs to the analog
switch that controls the analog inputs to the ADC con-
verter. Although these channels cannot be placed in the
Auto-Monitor mode, the host can request a direct conver-
sion.
Because these channels are designed to operate as
supply voltage monitors they are each tied into a program-
mable comparator. The comparator threshold voltage is
programmable and the polarity of the threshold is pro-
grammable. This allows very precise monitoring of under-
or over-voltage conditions. Paired with each of these
DEVICE OPERATION
channels is an over-current input (OC0 to OC3) that is
offset from its partner comparator by 50mV.
TIMER FUNCTIONS
WATCHDOG and LONGDOG
The SMD1108 has two programmable Watchdog timers
each with its own output (WDO# and LDO#) and a com-
mon reset input (WLDI). Both are independently program-
mable and both can be placed in an idle mode. See
Register 8C.
RST#
This reset output is intended to be used to drive the
backend logic. It is an active low open drain output that is
driven low whenever V
CC0
, V
CC1
, V
CC2
or V
CC3
is below its
programmed threshold and/or MR# is being driven low. It
will stay low for the duration of the fault condition or the
MR# low input and remain low for the duration of t
PURST
(the programmed reset pulse width) after removal of the
fault condition or MR# returning high. It will also be driven
low whenever an over-current condition is detected. See
Register 8C.
DLYD_RST#
This output is activated by the same set of conditions as
RST#. However, during a power-up operation it will not be
immediately asserted. As soon as power to one of the
V
CC0
/CH4 to V
CC3
/CH7 inputs is detected a time-out
sequence will be started. The time-out period is program-
mable and should be equal to or greater than the worst
case power-on skew between all the supplies being moni-
tored. If all of the supplies have not reached their threshold
before the time-out period, DLYD_RST# will be asserted.
DLYD_RST# can then be used to disable a voltage
sequencer such as the SMH4803A or SMH4804. See
Register 8D.
OUTPUTS
FAULT and HEALTHY
Two programmable outputs (active high or active low) that
will respond to programmed source activators. See Reg-
isters 8F and 90 through 95.
IRQs
The interrupt outputs are active low open drain outputs
that are driven low whenever one of the corresponding
monitor inputs senses an excursion beyond its pro-
grammed value. See Registers 88, 89, and 98 through 9F.
Table 1. Typical ADC Performance
2052 Table01
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