參數(shù)資料
型號(hào)： SMD1108F
廠商： Summit Microelectronics, Inc.
英文描述： 8-Channel Auto-Monitor ADC In System Programmable Analog (ISPA) Device
中文描述： 8通道自動(dòng)監(jiān)控ADC的在系統(tǒng)可編程模擬（ISPA）設(shè)備
文件頁(yè)數(shù)： 11/29頁(yè)
文件大小： 734K
代理商： SMD1108F
11
2052 2.0 10/05/01
SMD1108
Preliminary
SUMMIT MICROELECTRONICS, Inc.
mented by one. If the last address accessed (either a
Read or Write) was to address location n, the next Read
operation would access data from address location n+1
and increment the current address pointer. When the
SMD1108 receives the Slave address field with the R/W
bit set to 1 it issues an acknowledge and transmits the 8-
Bit word stored at address location n+1. The current
address byte Read operation only accesses a single byte
of data. The Master issues a NACK and generates a Stop
condition. At this point, the SMD1108 discontinues data
transmission.
Random Address Read
Random address Read operations allow the Master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the Master
issues a Write command which includes the Start condi-
tion and the Slave address field (with the R/W bit set to
Write) followed by the address of the word it is to read.
This procedure sets the internal address counter of the
SMD1108 to the desired address. After the word address
Acknowledge is received by the master, the master
immediately reissues a Start condition followed by an-
other Slave address field with the R/W bit set to Read. The
SMD1108 will respond with an Acknowledge and then
transmit the 8 data bits stored at the addressed location.
At this point, the Master issues a NACK and generates a
Stop condition. The SMD1108 discontinues data trans-
mission and reverts to its standby power mode.
Sequential READ
Sequential Reads can be initiated as either a current
address Read or random access Read. The first word is
transmitted as with the other byte Read modes (current
address byte Read or random address byte Read).
However, the Master now responds with an Acknowl-
edge, indicating that it requires additional data from the
SMD1108. The SMD1108 continues to output data for
each Acknowledge received. The Master terminates the
sequential Read operation with NACK and issues a Stop.
During a sequential Read operation the internal address
counter is automatically incremented with each Acknowl-
edge signal. For Read operations all address bits are
incremented, allowing the entire array to be read using a
single Read command. After a count of the last memory
address the address counter will rollover and the memory
will continue to output data.
SMB
ALERT
The function of the SMB
ALERT
output is similar to a
standard interrupt. Whenever one of the selected chan-
nels exceeds its limits the SMB
ALERT
pin will be driven low.
This action begins an exchange of information across the
2-wire interface that establishes the source of the inter-
rupt.
As shown in Figure 4 the SMB
ALERT
signal is driven low
and the host responds with the Alert Response Address
[0001 1001]. The SMD1108 will issue an Acknowledge
and then output its address, starting with the device type
identifier for the PSF registers [1001]. Following this the
SMD1108 outputs its bus address reflecting the biasing
of the A0, A1 and A2 pins. If the response to any bus
address option is selected and the pins are not biased the
read back will be [111]. The last bit is undefined.
At this point the Host should not issue an ACK, but
immediately generate a Stop condition. The SMD1108
will continue driving the SMB
ALERT
output low until the
Host responds back by generating a Start condition
followed by the SMD1108 address. The SMD1108 will
generate an ACK and release the SMB
ALERT
pin.
Figure 4. SMB
ALERT
Sequence
0
1
0
1
0
1
0
0
0
0
1
R
A
C
K
X
A
2
A
1
A
0
1
0
0
1
X
A
2
A
1
A
0
A
C
K
S
T
A
R
T
S
T
O
P
SCL
SDA
HOST
SMD1108
Alert Response Address
Device Address
Device Address
SMB
ALERT
2052 Fig04 1.0
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