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參數(shù)資料
| 型號： | SM8R-67025L-45/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 45 ns, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大小： | 257K |
| 代理商： | SM8R-67025L-45/883 |
M 67025
MATRA MHS
Rev. D (29/09/95)
17
AC Electrical Characteristics
over the Full Operating Temperature and Supply Voltage Range
WRITE
CYCLE
PARAMETER
M
67025–20
M
67025–25
M
67025–30
M
67025–35
M
67025–45
M
67025–55
UNIT
CYCLE
PARAMETER
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
UNIT
BUSY TIMING (For Master 67025 only)
tBAA
BUSY Access time
to address
–
20
–
25
–
30
–
35
–
35
–
45
ns
tBDA
BUSY Disable time
to address
–
15
–
20
–
25
–
30
–
30
–
40
ns
tBAC
BUSY Access time
to Chip Select
–
15
–
20
–
25
–
30
–
30
–
40
ns
tBDC
BUSY Disable time
to Chip Select
–
13
–
17
–
20
–
25
–
25
–
35
ns
tWDD
Write Pulse to data Delay
(1)
–
45
–
50
–
55
–
60
–
70
–
80
ns
tDDD
Write data valid to read
data delay (1)
–
35
–
35
–
40
–
45
–
55
–
65
ns
tAPS
Arbitration priority
set–up time (2)
5
–
5
–
5
–
5
–
5
–
5
–
ns
tBDD
BUSY disable to valid
data
–
Note 3
–
Note 3
–
Note 3
–
Note 3
–
Note 3
–
Note 3
ns
BUSY TIMING (For Slave 67025 only)
tWB
Write to BUSY input (4)
0
–
0
–
0
–
0
–
0
–
0
–
ns
tWH
Write hold after BUSY
(5)
15
–
17
–
20
–
25
–
25
–
25
–
ns
tWDD
Write pulse to data delay
(6)
–
45
–
50
–
55
–
60
–
70
–
80
ns
tDDD
Write data valid to read
data delay (6)
–
35
–
35
–
40
–
45
–
55
–
65
ns
Notes :
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with BUSY (For
Master 67025 only).
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) ot tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port-to-port
delay (For Slave, 67025 only)”.
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