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參數(shù)資料
| 型號： | SM8R-67025L-45/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | SRAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 45 ns, CPGA84 |
| 封裝： | PGA-84 |
| 文件頁數(shù)： | 10/23頁 |
| 文件大小： | 257K |
| 代理商： | SM8R-67025L-45/883 |
M 67025
MATRA MHS
Rev. D (29/09/95)
18
Timing Waveform of Read with BUSY (2, 3, 4) (For Master 67025)
Notes :
1. To ensure that the earlier of the two port wins.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
4. OE = L for the reading port.
Timing Waveform of Write with Port-to-Port (1, 2, 3) (For Slave 67025 Only)
Notes :
1. Assume BUSY = H for the writing port, and OE = L for the reading port.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
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