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參數(shù)資料
| 型號(hào)： | SM320C6701GJCA16EP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 32-BIT, 166.67 MHz, OTHER DSP, PBGA352 |
| 封裝： | 35 X 35 MM, PLASTIC, BGA-352 |
| 文件頁數(shù)： | 37/62頁 |
| 文件大?。?/td> | 894K |
| 代理商： | SM320C6701GJCA16EP |
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SM320C6701EP, SM320C6701MECHEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A MAY 1998 REVISED APRIL 2004
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
RESET TIMING
timing requirements for reset (see Figure 25)
NO.
C6701-120
C6701-167
UNIT
NO.
MIN
MAX
UNIT
1
tw(RESET)
Width of the RESET pulse (PLL stable)
10
CLKOUT1
cycles
1
tw(RESET)
Width of the RESET pulse (PLL needs to sync up)
250
s
This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.
This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may
need up to 250
s to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted
to ensure proper device operation. See the clock PLL section for PLL lock times.
switching characteristics during reset§ (see Figure 25)
NO.
PARAMETER
C6701-120
C6701-167
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
2
tR(RESET)
Response time to change of value in RESET signal
1
CLKOUT1
cycles
3
td(CKO1H-CKO2IV)
Delay time, CLKOUT1 high to CLKOUT2 invalid
1
ns
4
td(CKO1H-CKO2V)
Delay time, CLKOUT1 high to CLKOUT2 valid
10
ns
5
td(CKO1H-SDCLKIV)
Delay time, CLKOUT1 high to SDCLK invalid
1
ns
6
td(CKO1H-SDCLKV)
Delay time, CLKOUT1 high to SDCLK valid
10
ns
7
td(CKO1H-SSCKIV)
Delay time, CLKOUT1 high to SSCLK invalid
1
ns
8
td(CKO1H-SSCKV)
Delay time, CLKOUT1 high to SSCLK valid
10
ns
9
td(CKO1H-LOWIV)
Delay time, CLKOUT1 high to low group invalid
1
ns
10
td(CKO1H-LOWV)
Delay time, CLKOUT1 high to low group valid
10
ns
11
td(CKO1H-HIGHIV)
Delay time, CLKOUT1 high to high group invalid
1
ns
12
td(CKO1H-HIGHV)
Delay time, CLKOUT1 high to high group valid
10
ns
13
td(CKO1H-ZHZ)
Delay time, CLKOUT1 high to Z group high impedance
1
ns
14
td(CKO1H-ZV)
Delay time, CLKOUT1 high to Z group valid
10
ns
§ Low group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
High group consists of:
HINT.
Z group consists of:
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
HRDY is gated by input HCS.
If HCS = 0 at device reset, HRDY belongs to the high group.
If HCS = 1 at device reset, HRDY belongs to the low group.
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