參數(shù)資料
型號： SM320C6701GJCA16EP
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 32-BIT, 166.67 MHz, OTHER DSP, PBGA352
封裝： 35 X 35 MM, PLASTIC, BGA-352
文件頁數(shù)： 29/62頁
文件大?。?/td> 894K
代理商： SM320C6701GJCA16EP
SM320C6701EP, SM320C6701MECHEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSOR
SGUS042A MAY 1998 REVISED APRIL 2004
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16)
NO.
C6701-120
C6701-167
UNIT
NO.
MIN
MAX
UNIT
7
tsu(EDV-SSCLKH)
Setup time, read EDx valid before SSCLK high
3.6
ns
8
th(SSCLKH-EDV)
Hold time, read EDx valid after SSCLK high
1.5
ns
switching characteristics for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 16 and Figure 17)
NO.
PARAMETER
C6701-120
C6701-167
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1
tosu(CEV-SSCLKH)
Output setup time, CEx valid before SSCLK high
1.5P 4.5
ns
2
toh(SSCLKH-CEV)
Output hold time, CEx valid after SSCLK high
0.5P 2.5
0.5P 2
ns
3
tosu(BEV-SSCLKH)
Output setup time, BEx valid before SSCLK high
1.5P 4.5
ns
4
toh(SSCLKH-BEIV)
Output hold time, BEx invalid after SSCLK high
0.5P 2.5
0.5P 2
ns
5
tosu(EAV-SSCLKH)
Output setup time, EAx valid before SSCLK high
1.5P 4.5
ns
6
toh(SSCLKH-EAIV)
Output hold time, EAx invalid after SSCLK high
0.5P 2.5
0.5P 2
ns
9
tosu(ADSV-SSCLKH)
Output setup time, SSADS valid before SSCLK high
1.5P 4.5
ns
10
toh(SSCLKH-ADSV)
Output hold time, SSADS valid after SSCLK high
0.5P 2.5
0.5P 2
ns
11
tosu(OEV-SSCLKH)
Output setup time, SSOE valid before SSCLK high
1.5P 4.5
ns
12
toh(SSCLKH-OEV)
Output hold time, SSOE valid after SSCLK high
0.5P 2.5
0.5P 2
ns
13
tosu(EDV-SSCLKH)
Output setup time, EDx valid before SSCLK high
1.5P 4.5
ns
14
toh(SSCLKH-EDIV)
Output hold time, EDx invalid after SSCLK high
0.5P 2.5
0.5P 2
ns
15
tosu(WEV-SSCLKH)
Output setup time, SSWE valid before SSCLK high
1.5P 4.5
ns
16
toh(SSCLKH-WEV)
Output hold time, SSWE valid after SSCLK high
0.5P 2.5
0.5P 2
ns
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
相關(guān)PDF資料
PDF描述
SM320C6701GLPW16 32-BIT, 167 MHz, OTHER DSP, CBGA429
SM320C6701GLPS14 32-BIT, 140 MHz, OTHER DSP, CBGA429
SM320C80GFM40 64-BIT, 80 MHz, OTHER DSP, CPGA305
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SM320C6701GLPS16 制造商:Texas Instruments 功能描述:DSP,1000 MFLOPS,167MHZ,-40C/+90C,C-BGA - Trays
SM320C6701GLPW14 制造商:Texas Instruments 功能描述:DSP Floating-Point 32-Bit 140MHz 1120MIPS 429-Pin CFCBGA Tray 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:TISSM320C6701GLPW14 FLOATING POINT DSP
SM320C6701S14 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SM320C6701S16 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SM320C6701W14 制造商:TI 制造商全稱:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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